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Old 14th April 2010, 07:47 PM   #1
bwaslo is offline bwaslo  United States
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Default Power GaN FETS now at DigiKey...

I tried to post the pdf data file, but rejected because too big.

See Digi-Key - 917-1005-6-ND (Manufacturer - EPC1011)

Is this significant for ClassD development? Not sure how to mount one of these, though. Price isn't bad at all....

data sheet link:
http://epc-co.com/epc/documents/data...heet_final.pdf

Last edited by bwaslo; 14th April 2010 at 07:52 PM. Reason: add data sheet link
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Old 15th April 2010, 08:41 PM   #2
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Wow
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Old 16th April 2010, 05:52 PM   #3
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Looking promising, but their casing design is really not developer friendly.
Also I wish they would have specified their body diodes more precise, or can it be true that their body diode really has a reverse recovery charge below the nC range?
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Old 16th April 2010, 06:00 PM   #4
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...have to correct myself...
It isn't a casing. It's a die.
Even I would love to change my current plans -
I tend to say: 'No problem' = No, I cannot. It's a problem.
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Old 16th April 2010, 06:00 PM   #5
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Well that's the figure for the 200V 12A switch as well, so I don't think it's a mistake.

I think to really get out of these what is possible you can't put it in a case, especially for the price.
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Old 16th April 2010, 06:21 PM   #6
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Well, for class D in the range of some single kW and switching frequencies up to 1 MHz, I could survive with TO-220 and would love TO-252 (D-pack). The resulting inductances can be handled without to much headache.
But the body diodes of Si-MosFets are a torture for my naive soul, and placing a series schottky + additional fast freewheeling is also not charming at all.
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Old 16th April 2010, 07:44 PM   #7
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According to the docs in their "Tools and Design Support" pages,
http://epc-co.com/epc/documents/prod...ndamentals.pdf

"With zero bias gate to source, there is an absence of electrons under the gate region. As the drain voltage is decreased, a positive bias on the gate is created relative to the drift region, injecting electrons under the gate. Once the gate threshold is reached, there will be sufficient electrons under the gate to form a conductive channel. The benefit to this mechanism is that there are no minority carriers involved in conduction, and therefore no reverse recovery losses. While QRR is zero, output capacitance (COSS) has to be charged and discharged with every switching cycle. For devices of similar RDS(on), GaN transistors have significantly lower COSS than silicon MOSFETs. As it takes threshold voltage to turn on the GaN transistor in the reverse direction, the forward voltage of the “diode” is higher than silicon transistors."

So apparently QRR is actually zero (not that I actually understand why).

There is another doc, http://epc-co.com/epc/documents/prod...ing_GaN_r4.pdf that shows some circuit board patterns for using the parts. Apparently the solder-balled chip "package" can be soldered down using SMT techniques, though heatsinking doesn't look easy to accomplish (but efficiently coupled once done).

The rather low maximum Vgs rating is also intimidating. I imagine there will be a small jar of burned out devices resulting before an acceptible design is reached, at least by someone like me...
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Old 16th April 2010, 07:58 PM   #8
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Here is a diagram (from their powerpoint presentation on the website) of how board connection/heatsinking is done. You push the heatsink right against the (insulated) silicon back substrate. I guess that's not too far off from how Pentium chips are heatsinked, maybe doable by DIY.

Click the image to open in full size.
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Old 16th April 2010, 08:18 PM   #9
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....hm... I am already at my biological limit, when soldering a LT1711, but this would be definitely one step beyond.
Might be possible to get it running for some measurements to satisfy curiosity, but I doubt, that my DIY handling would result in a reliable construction.
Nevertheless - temptating.
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Old 16th April 2010, 08:21 PM   #10
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A good challenge for the DIYer would be arranging to have the substrate surface all in a plane after soldering for compatibility with a hard thermal interface. Maybe if you were only losing a few watts per transistor, maybe normal for switching applications, a pad of some kind could be reliably used. The CPU analogy is good in the sense that it's a mammoth die (or four) only losing tens of watts peak each. Maybe a board house capable of handling flip chips at all would be able to handle decent coplanarity, but the usual surface mount equipment couldn't do it.

Last edited by Andrew Eckhardt; 16th April 2010 at 08:23 PM.
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