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Old 11th March 2010, 08:55 AM   #1
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Default Self Oscillating (Oscillating Calculations) Help!

Hi all

After searching almost all the threads I was unable to find any form of calculations regarding the calculations of the switching frequency in a Self Oscillating amplifier, I still donít understand how designs came to the selected component values?

Can someone with knowledge please show me how to achieve this? I have basic elementary electronics experience and have access to a simulation software and a scope, I would love to use the self oscillating topology but Iím really stuck Iím not willing to copy and paste other peoples work and build it I feel itís just cheating.

P.S I have read ucd paper by Bruno Putzeys but there are no calculations around component selection.

http://www.ciaudio.com/ucd_aes.pdf



Thank you in advance.
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Old 11th March 2010, 10:11 AM   #2
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With no signal and 0V output, the self oscillating frequency will be the frequency where the phase lag due to the output filter, plus the phase lag due to propagation delay (usually from comparator, level shift and gate drive), plus the phase lead/lag due to compensation networks equals 180 degree. Plot the sum of these phase shifts with the help of a simulator and you will get what you want. There is no simple equation to do it.

Without any compensation, the oscillating frequency is going to be too low, so one or more RC are usually added in parallel with feedback resistor to produce some phase lead and move the 180 degree crossing point to a higher frequency.

It's not a good idea to fed the high frequency component of the output signal, the one that produces self oscillation, through op-amps, because they add both delay and phase shift at these high frequencies, and they can distort the shape of the carrier residual, which may contain components as high as 10Mhz when the output of the amplifier approaches the rails. Split feedback may be used to fed the high frequency component direcly to the comparator and the audio frequencies to op-amp integrator(s) to increase open loop gain.
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Last edited by Eva; 11th March 2010 at 10:15 AM.
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Old 11th March 2010, 01:03 PM   #3
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I got that i think

No simple math uhmm i thought as much no wonder everyone 'shys' off when it comes to the caluclations. Control loop theory will help alot here i can model that in ewb 8 with ideal op amps and voltage control switchs.

I will post my progress here as i discover findings in the simulator.

Thanks eva,
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Old 12th March 2010, 03:26 AM   #4
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Actually Eva, it's when the total phase shift crosses 360 degrees and thus becomes positive feedback, as with any phase oscillator, basic stuff.

The only stipulation is that it occurs while the gain is at or above unity and of course you also want to make it happen at a frequency that provides good attenuation of the carrier for full range audio, why you can't just use a resistor. It's also nice to have it cross steeply enough to minimize frequency modulation.
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Old 12th March 2010, 04:17 AM   #5
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Your both right. The total phase shift has to be 360 degrees but because the output goes into the negative input thats an automatic 180, so the rest of the cct only needs 180 as EVA said.
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Old 12th March 2010, 06:13 AM   #6
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Oscillation frequency will drop progressively as the output approaches the rails. A drop ratio around 2:1 at -1dB seems to work best. THD is related to te way in which frequency is reduced, which is related to the "phase margin" and the shape of phase shift between minimum oscillation frequency and idle oscillation frequency.

There are optimum phase shift patterns/shapes resulting in optimum frequency drop and minimum THD, and I think Bruno found them I think I found a good approach too. These patterns seem to be related to keeping constant carrier residual amplitude. In these amplifiers carrier residual plays the same role as the sawtooth in clocked modulators, so it has to be handled with care.

Frequency drop results in a great reduction in switching losses without penalties.
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Last edited by Eva; 12th March 2010 at 06:21 AM.
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Old 12th March 2010, 07:43 AM   #7
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No penalties? No such thing as compromise or trade-offs in engineering? Such absolutes are where the discussion ends and the marketing begins.
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Old 12th March 2010, 07:37 PM   #8
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Keeping the amplitude of ucd ripple seems so important to linearity because the carrier is generally not a triangle.
Inductance drop at higher current affects the amplitude output ripple as well which harms the linearity of ucd modulator. You cannot compensate for that effect at reactive (and unknown) load.
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