LTspice delay

Status
This old topic is closed. If you want to reopen this topic, contact a moderator using the "Report Post" button.
A Class-d amp can be described simplified in the time domain as an amplification or gain, a delay of 1 sample freq and the output filter.

How do you model the delay in LTspice??

Have tried to use a transmission line, but it doesent really work ...
What is needed is perfect (same delay at all feq) delay of e.g. 200nS in the time domain.

I want this to be able to model different feedback network in the frequency domain.

Can anyone help????

Thanks in advance and best regards Baldin
 
I don't use LTspice, but in the old version of Pspice that I use analog delay lines need a characteristic impedance to be specified, and they need to be driven and loaded exactly from that impedance to avoid problems, for example 100 ohm. Voltage controlled voltage sources may be used for input and output buffering.

I didn't find a better way to do it, as the other type of delay line available in my PSpice is digital and gives a lot of trouble with A/D conversion.
 
Hi Eva

Playing a bit more with the Transmission line in LTspice, and terminating it correctly in both ends, actually seems to work.

I think it was partly not having the right termination and partly not getting what I expected, causing the problems :) ... I now use 100 ohm in both ends, and 100 ohm line, and added a buffer on the receiving end.

Thanks and best regards Baldin ;)
 
It should be sufficient to terminate the output side with the same Z that you have specified for the TL. Effective drive impedance should not change the shape, but result in a voltage divider of drive impedance and load.
So far my LT Spice always handled the TL perfectly fine.
 
Hi ChocoHolic

Well, that was also my fault ... I did not load it at the output with the same impedance as specified for the line .....
On the other hand, it overall didn't look as expected ;) ...... so I thought it was only because the modeling was wrong .... some was, some was my thinking :)

As the moment I'm strugleing with my design stopping to oscillate when not loaded (real life test, not simulated) ... funny thing is I have one oscillator board with a MXL1016 that work without problem, but the LT1711 board stops whan the load is removed ... and will not start without load either (and mosfets heat up :() .... ... one difference is of cource the output being 0/5V on the MXL, and +-5V on the LT ..... but going through the rest of the amp this shouldn't matter!!
 
...too bad. Pin5 would have been such a simple solution...
Anyway, good luck!

P.S:
You have a nice home page! ...and a seperate room for the home theatre!!! *envy*

Yes, that would have been a fast solution :) ..... I have had trouble getting it to start from the begining. Solution was to make an inner loop, that is only dominant at start up, feeding back from the comparator to the integrator instead of from the mos output.

About the homepage: Thanks :) ..... I don't get it updated that often though :(

About the separate room: Yes I know it a bit crazy ... housing prices and all .... but it's just so good :D ...... I'm spending a fair bit of time there relaxing .... a bit more movies, than music to be honest ;)
Doing something about the room acoustics, is just such an improvement, and the only way to get full benefit of your speakers ....
 
In LTspice the properly configured T-line element (ideal lossless transmission line) provides an ideal delay with higher accuracy and better computational efficiency than the b-source and it also works equally well in the frequency domain (.ac analysis).

The circuit with the unloaded output may be not oscillating because of differences in comparator gain and because of parasitic elements in the output filter. The LT part has about 80dB of open loop gain. The phase shift provided by the output filter approaches 180 degrees, but won't quite get there because of the parasitics. It is possible that there isn't enough delay from the comparator to provide the additional phase shift required for oscillation before the loop runs out of gain. Inadvertent hysteresis can also sometimes inhibit start up.

It is also possible that the circuit is actually oscillating at very high frequency and you are just not seeing it (this could explain the heating).

To work properly at a well defined frequency this sort of circuit should have lots of excess gain and cross 360 degrees of loop phase shift with a steep slope rather than very gradually sneak up on that point. Maybe the circuit needs some additional phase shift networks to better control the oscillation frequency point.

Can you provide a better description of the details of your circuit?
 
Hi analogspiceman

I'm trying to do a good approximation in LTSpice of different pwm amps to test out different modulators.
I have now found that using the Schmitt model seems to work really good at representing the output stage including the necessary delay.
Take a look at the UcD model here ..... anyone find any faulty conceptions in this??

Best regards Baldin ;)
 

Attachments

  • XcD Simulation - UcD.zip
    1.6 KB · Views: 164
A realistic simulation of dead time distortion requires a realistic model of the output stage. This must include the small inductances in the high current path that affect the drive signal, must include realistic gate drain capacitances in the MOSFETs and must include realistic MOSFET body diode models.

The good news is that LTspice is capable of all this and more all the while running at reasonable speed, but the bad news is that few LTspice users are capable of providing LTspice with the correct input.

For such a study, I would use simplified behavioral models for everything from the input to the driver IC output (the comparator and driver IC parts making good use of LTspice's a-devices). The bit from the driver to the output inductor would need accurate models for the pull down PNPs and for all the circuit trace inductances in the high current path. -- a.s.
 
'm hoping someone here can educate me on how to work through a simple
problem in LTSpice. (I'll also try the Yahoo group, but I'm having troubles
with that web page just now.)

I have a simple circuit with two NOR gates, a resistor, and a capacitor.
(Some of you might recognize it from a recent s.e.d posting.) I've appended
the LTSpice .asc contents below. When I try simulating it, I get this
error:
"Analysis: Timestep too small; initial timepoint: trouble with
or-instance a1".

None of the obvious options on the simulation command seem to make any
difference. One possibility is that I'm not using the OR gate correctly; per
the online help, I'm leaving unused inputs unconnected. But I also tried
grounding the unused inputs, and that didn't seem to make much difference.
=========================
magnetic latching relay
Bathmate UK
 
Hi Baldin,

You recently asked about an LTspice model of a UcD type amplifier with variable dead time such that you might study how it influences the THD of the audio output. Today I made up a reasonably accurate, but still fast running model for LTspice. Not only does it have a comparator-driver section with variable delay time, rise time, dead time and output drive levels (voltage and current), but it also has a fully discrete element power stage that includes most of the important inductances.

I haven't played with it very much to study THD, but I ran it at moderate load with and without dead time with these results:

THD=0.017% with zero dead time
THD=0.096% with 85ns dead time

A GIF graphic and zipped file of the LTspice schematic are below:
 

Attachments

  • UcD_Dead_Time.gif
    UcD_Dead_Time.gif
    42.1 KB · Views: 393
  • UcD_Dead_Time.zip
    2.6 KB · Views: 147
Status
This old topic is closed. If you want to reopen this topic, contact a moderator using the "Report Post" button.