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Old 21st September 2009, 09:32 AM   #11
Pafi is offline Pafi  Hungary
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Quote:
the 'scope doesn't lie:
Actually it does. Probe capacitance makes rise time much higher, especially if you use 1:1 probe. Try 1:10, and 1k pull-up! (But I don't know why you need +/-12 V PWM.)
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Old 21st September 2009, 12:35 PM   #12
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aha! thanks Pafi! you're absolutely right! not sure how that slipped past me. rise time is greatly improved now. (+/-12V pwm is just really because it's a first attempt and i wanted to try directly driving the FET gates with the comparator... will the comparator output not be capable of supplying the required gate current to directly switch the FETs? (N-ch and P-ch complimentary.))

~ brad.
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Old 21st September 2009, 12:48 PM   #13
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oh... i guess i kind of answered my own question... the 1300pF input capacitance of the FET would cause the same sort of slow rise time as the scope probe capacitance, right? (you'll have to excuse my lack of expert knowledge here, the closest i've come to class-d is a boost converter for nixies... )

thanks again for all the help,
~ brad.
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Old 21st September 2009, 04:29 PM   #14
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ok, i've read a bit more (and am still reading, lol) and it looks like it's back to the spice drawing board for some gate drivers... will come back with a schematic that seems to simulate well.

thanks,
~ brad.
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Old 21st September 2009, 10:27 PM   #15
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Question FIRST REVISION of discrete gate driver

ok, here's my first rough idea of what my gate driver should look like. the output FETs are IRF9540 and IRF640, since this is a first design and i'd like to stick with the simple for now.

spice shows interesting results, but i'm still not happy with the gate rising-edge waveforms... any optimizations or recommendations here?

oh and, since this is completely off the subject of the triangle generator, should this be in a new topic?

thanks,
~ brad.

p.s.: thumbnails below: mpsa42/mpsa92 emitters, mosfet gates, pre-filter output.
Attached Images
File Type: png vemitter01.png (24.6 KB, 133 views)
File Type: png vgates01.png (26.7 KB, 130 views)
File Type: png vout01.png (19.9 KB, 126 views)
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File Type: pdf driver.pdf (7.2 KB, 48 views)

Last edited by geekysuavo; 21st September 2009 at 10:54 PM. Reason: ambiguous images...
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Old 22nd September 2009, 04:24 AM   #16
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well, the simulation and real life differ, i'm not surprised.

i guess it would be smart to head back to the drawing board completely, maybe by trying the gate driver ICs from IRF, considering its ease of implementation...

well foo, everything was working until i got to the gate drivers...

~ brad.
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Old 22nd September 2009, 10:32 AM   #17
81bas is offline 81bas  Germany
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Quote:
Originally Posted by geekysuavo View Post
ok, here's my first rough idea of what my gate driver should look like. the output FETs are IRF9540 and IRF640, since this is a first design and i'd like to stick with the simple for now.
The generall idea is OK. But Dgh must be reversed. And this schematic will produce 24V pulses on the mosfet gates (although usually the limit is 20V).

Also, the using of IR2110 is a common way to implement the class D output stage. And it will give you much more possibilities to made the next steps in your expremeting and education
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