Difference between self oscillating and non-self oscillating D-amp.

Status
This old topic is closed. If you want to reopen this topic, contact a moderator using the "Report Post" button.
These simulations illustrate my approach to class D. It's a full range amplifier which self oscillates at 240khz with no signal.

First picture:
Green trace is output voltage with 4 ohm slightly inductive load (simulating a high frequency voice coil) at 1dB below clipping. Note how well one cycle of 4khz sine wave is shaped with just 40 switching events, and most of them happen when output current is low, only a few happen with high current. THD is below 0.1%, and it becomes much lower at -2dB and again much lower below -3dB. It also becomes lower with a purely resistive load or no load at all, semi-inductive load is the worst case.

Red trace is output waveform after going through a 25Khz brickwall filter. There are no traces of ripple, all the hash is way above 25khz.

Blue trace is the input signal to the comparator showing constant "triangle wave" amplitude, regardless of varying switching frequency.

Second picture:
Frequency response (and group delay), it's ruler flat to 20khz (less than 0.1dB deviation, -3dB at 40khz), regardless of load impedance, and regardless of the low switching frequencies involved (40 switching events at 4khz gives 160khz effective, in other words, a very efficient amplifier).
 

Attachments

  • 4KHZ40PT.GIF
    4KHZ40PT.GIF
    39.5 KB · Views: 509
  • 4KHZ40P2.gif
    4KHZ40P2.gif
    21.7 KB · Views: 497
These simulations illustrate my approach to class D. It's a full range amplifier which self oscillates at 240khz with no signal.

First picture:
Green trace is output voltage with 4 ohm slightly inductive load (simulating a high frequency voice coil) at 1dB below clipping. Note how well one cycle of 4khz sine wave is shaped with just 40 switching events, and most of them happen when output current is low, only a few happen with high current. THD is below 0.1%, and it becomes much lower at -2dB and again much lower below -3dB. It also becomes lower with a purely resistive load or no load at all, semi-inductive load is the worst case.

Red trace is output waveform after going through a 25Khz brickwall filter. There are no traces of ripple, all the hash is way above 25khz.

Blue trace is the input signal to the comparator showing constant "triangle wave" amplitude, regardless of varying switching frequency.

Second picture:
Frequency response (and group delay), it's ruler flat to 20khz (less than 0.1dB deviation, -3dB at 40khz), regardless of load impedance, and regardless of the low switching frequencies involved (40 switching events at 4khz gives 160khz effective, in other words, a very efficient amplifier).

Hi,
You know that I appreciate your work.:)
ok, now I can see the same simulation with input at 10Khz and 20KHz? (First pic).
see what is the phase shift:D
 
Single phase Vs Four Phase interleaved Class-D

As i am currently developing a project for interleaved 4 phase modulator for class-D.....have a look at some simulation result of output.
Sinewave =1k & SWFQ=250khz, the resultant carrier ripple in 4-phase is 250k X 4= 1MHZ which is easy to filter using small inductors.
 

Attachments

  • 1phase.jpg
    1phase.jpg
    133.7 KB · Views: 453
  • 4phase.jpg
    4phase.jpg
    129 KB · Views: 404
These simulations correspond to 10khz and 20khz output 1dB below clipping, load is 4 ohm in series with 33uH (at 20khz load impedance is 8 ohm, this is my high frequency voice coil modelling). Output filter resonates at 20khz.

Note that at 20khz there is much less oscillating frequency drop than expected, it's not going below 200khz. Another "undocumented feature" of self oscillation is being taken advantage of. Since output filter resonates at 20khz and it's sized for not reaching damped operation until load goes below 2.5 ohm, there is additional gain around 20khz, approx 5dB with 33uH in series with 4 ohm load. The extra gain results in much less duty cycle swing required to reach full output (and higher open loop gain), and thus, much less oscillation frequency drop. 11 switching events are required for one cycle of 20khz sine wave. If high frequency load impedance is increased to 8 or 16 ohms (typical values), things improve further (extra points per cycle down to 10khz).

Also, note the absence of hash on the 25khz brickwall-filtered output waveform (red trace), which is not in phase with amplifier output due to the high group delay of the filter (8th order).

To workhorse: Are so many switching events really required?
 

Attachments

  • 10KHZ_FR.gif
    10KHZ_FR.gif
    36.5 KB · Views: 398
  • 20KHZ_FR.gif
    20KHZ_FR.gif
    44.6 KB · Views: 217
Last edited:
The printing "window" is synchronized with input waveform, not with output waveforms. At 4khz printing is delayed 250us (one cycle) and at 10khz and 20khz 100us (one and two cycles) to hide circuit startup behaviour. Amplifier output lags approx 10us with respect to input, and then, the brickwall filtered reference output lags another few dozen us. That's why the waveforms are not "in phase" with the simulation window.
 
The printing "window" is synchronized with input waveform, not with output waveforms. At 4khz printing is delayed 250us (one cycle) and at 10khz and 20khz 100us (one and two cycles) to hide circuit startup behaviour. Amplifier output lags approx 10us with respect to input, and then, the brickwall filtered reference output lags another few dozen us. That's why the waveforms are not "in phase" with the simulation window.

very interesting, I saw well.
result is very similar to MXD-modulator, the difference is that I clean every cycle because compare post-filter with pre-filter in relation to the input signal. this system does not apply delay between input and output.
certainly not well explained in two words.
 
Disabled Account
Joined 2008
Self oscillating Class D is more than just UCD.

This is my take (not UCD).

Parts of the schematic are posted on another site. :)

Cheers
 

Attachments

  • Class d Transient 1k sinus comp inp.pdf
    140.6 KB · Views: 131
  • Class d Transient 1k sinus.pdf
    60.5 KB · Views: 150
  • Class D AC.pdf
    17.7 KB · Views: 268
  • Class d Transient 20k sinus.pdf
    20.7 KB · Views: 98
  • Class d Transient 20k sinus comp inp.pdf
    31.4 KB · Views: 153
  • THD class d.pdf
    6.3 KB · Views: 207
Disabled Account
Joined 2008
Hey all,

I'm still a little confused with regard to self-oscillating designs. Would anyone be able to answer this: say you have a design that self-oscillates at 200 kHz with no input signal. What points in the circuit are in oscillation? Is the power stage oscillating at 200 kHz?

http://www.ciaudio.com/ucd_aes.pdf

I was looking at this short presentation on UcD. Page 3, at the top shows a simplified model. Now, I can see how you would use the comparator to make an oscillator using the positive input, but I don't understand how the oscillation includes the power stage, and the inductor.

Can anyone shed some light on the waveforms present at different points, at idle perhaps?

Thanks guys,

Jim
 
With a self-oscillating amplifier, at its operating frequency (whatever that may be or however it may vary), loop gain must always be exactly one (0dB) and loop phase must always be exactly 360 degrees. This is the basic theoretical requirement for sustained oscillation.

Loop gain is the product of the gain in the forward path from amplifier input, through the power stage and out through the output filter all multiplied by the gain in the feedback path from the output back again to the input (this gain is usually quit a bit less than one). Loop phase is the phase shift of same signal around this loop. Note that passing the signal through an inversion point flips the phase through that point by 180 degrees (the gain is unchanged).

Although they generally have differing amplitudes and phases, all points around this loop are oscillating at the same frequency, so, yes, the power stage is oscillating, even with no input.

In this type of power oscillator there always is excessive loop gain available, but output stage saturation (at the supply rail voltages) always limits the loop gain automatically to be exactly unity regardless of the particular oscillation frequency. Therefore, it is the phase shift around the loop that determines the frequency of oscillation.

Typically 180 degrees of this phase shift comes from passing the signal through the inverting input and another 180 degrees of lag comes from the LC output filter. This is too much phase shift (already approaching 360 total), so the feedback network usually has a capacitor to provide phase lead (up to 90 degrees), such that these elements combine for an overall phase shift at the operating frequency that is still short by 75 degrees or so.

This missing phase shift is provided by the combination of power stage switching delay and by one or two identical small RC low pass networks placed in the path somewhere between the amplifier input and the power stage. The RC corner frequency is very high, perhaps just a little higher than the operating frequency.

This all works much like the classic digital gate 3-RC-stage phase shift oscillator, except that the output power levels are much higher.
 
As i am currently developing a project for interleaved 4 phase modulator for class-D.....have a look at some simulation result of output.
Sinewave =1k & SWFQ=250khz, the resultant carrier ripple in 4-phase is 250k X 4= 1MHZ which is easy to filter using small inductors.

Can you please explain how do you interlive the fases and still have a sellf oscilatting strategy. I thought about this and i can't get it ...
 
Status
This old topic is closed. If you want to reopen this topic, contact a moderator using the "Report Post" button.