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Old 3rd July 2009, 08:55 PM   #1
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Default bridged UcD-like hybride

Main idea was to force input`s Smidt triggers (inside gate driver) generate small dead time due to limited slew rate of comparator`s output thanks to "parasitic" C1.

What do you think about that? Would it works or there is something wrong with A,B,C,D points connection or something else?

Anyway, I have try to simplify entire design as much as possible, including power supply. If input comparator havn`t enought gain it can be transformed to common emitter-common base-common base, probably with current mirror as load.
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Old 5th July 2009, 11:05 AM   #2
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Hi Kuzmenko,

Yes, your idea is good and you can reach the fully working version of your idea with a bit modifications. For a long time I gave up working on electronics. But, I am following forum to know what the others are doing.

I have now a working hybrid UCD amp ( 6 channel and not finished yet). I used ordinary IRF540N mosfets and obtained 32ns rise/fall times on the output. Any way some hints; 1st use better mosfet drivers like IR2111, HIP2111, ISL2111 or more known IR2110. 2nd; use the complete comparator section of UCD amp up to mosfet turn on transistor (BC857B) for both H and L side and then connect them with 1K sthut off resistors to H&L in of two mosfet driver. Another good idea to make the comparator as a daughter board and mosfet drivers on the main board. Pherhaps Hypex do this. I do not know. But, I will work completely.

I used a bit hard to find mosfet driver called MAX5048A from maxim instead of PBSST5140T shown on NXP UM10155. Also ommit the caps (10uf) in the feedback path of your shematic. U can simulate it with SWcad from Linear technology.
Regards

NB: Use Cmos input drivers not TTL. Otherwise you have to put some voltage drivers on the input of driver if you use TTL versions and the voltage driver effect your dead time. This will cause more dead time adjust components on your circuit. Believe me I tested same circuit with MAX5048B(TTL version) and got pain with dead time adjust!
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Old 5th July 2009, 06:04 PM   #3
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Hm-m.. it seems that this idea would not work as thoughts
With this C1 we delayed high- side switch opens and low-side switch closing by the SAME TIME. I.e. possibility of shoot- throught is remain, just delayed by couple nsec
So, now i think about traditional R||diode-C delaying circuits on HI and LO inputs.
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Old 5th July 2009, 08:27 PM   #4
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Default Forget RDC network for delay

Kuzmenko,

I enclosed a part of my implementation. Here R1 is the dead time adjust resistor which is very useful for this issiue. I used one resistor with a PTC to obtain a temperature compansated dead time control. Any way I will open a new topic or go on the old topic here soon.

Regards
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