To Clock or not to Clock!

[analogspiceman]

When you model PWM with linear elements, then you must assure that signals don't violate Shannon's theorem. A step signal is not a usable test-signal. Take a sine wave as input of the modulator with smaller (much smaller for clarity) freq than fs/2, and you will find that in the spectra of output signal the fundamental component will have perfectly zero phase-shift!

Sampling itself never introduces delay. What does (in mixed, discrete and continuous time systems) is zero order holder (or any other reconstruction filter)!

Naturally sampled real time PWM is a causal process (a system with output and internal states that depends only on the current and previous input values). Therefore, at least for small signal perturbations, the sampling portion will always devolve to a zero order hold (or worse). With such causal sampled systems the excess phase shift at half the carrier frequency must be at least 180 degrees.

For circuit analysis, a reasonable continuous linear approximation of the sampling process can be made in various ways (e.g., by adding a delay block or a few high frequency poles). Of course, at sufficiently low frequencies, the sampling process and/or any of its approximations will contribute near zero phase shift.

If you were right, total phase-shift in a self-oscillating amp at switching freq in the whole loop would be: 180 (invert) + almost 180 (LC LPF) + 180 (delay of sampling) + 36 (220 ns delay of miscellaneous stages at fs=400 kHz) - 30 (phase shift of feedback network) = 540 degrees. Oops! This doesn't work. There should be 360 degrees of phase shift for oscillation.

You may be confusing the situation that leads to self oscillation verses the situation for a small signal perturbation of the zero crossing at the comparator input of the large signal self oscillation. The nonlinear effects make this very tricky analytical territory to traverse.

With a UcD type circuit, almost all of the circuitry around the feedback loop is linear. The exception is the nonlinear section from the the comparator's input to output of the MOSFET switches. This is where it is problematic to recognize the gain and phase of the signal at the amplifier's switching frequency. Here, these signals aren't sine waves, so how can gain have any meaning in the linear, small signal sense?

The "trick" is to first mentally pick out the fundamental Fourier components of the signals appearing at the comparator and at the output (which is always gain limited via saturation). From this Fourier analysis point of view, the comparator/output stage appears completely linear because there are only perfect, unsaturated sine waves components remaining. At a single frequency, gain and phase always make sense. (IMO, this process is made easiest if delay is pulled out as a separate effect.)

For example, consider the UcD at idle (i.e., no input). Then the signal at the comparator looks more-or-less like a small sine wave and the output signal is a square wave that is (except for a small delay) exactly in phase with the comparator input. But what is gain?

Since the UcD at quiescence is just a power oscillator, neither decaying nor increasing in amplitude, we know that total loop gain must be exactly unity. Now calculate the attenuation around the rest of the loop due to the output filter and other R/C networks before the comparator. The effective gain of the saturating comparator/output stage gain must make up exactly this amount of loss (the output square wave is fixed in size by the power supplies).

The other condition required to build a stable oscillation (now that's an oxymoron) besides unity gain around the loop is reinforcing phase (i.e., 0, 360, 720, etc. degrees). Since loop gain will always self adjust via output saturation at any operating frequency, it must be the loop phase characteristics that control the exact operating frequency. In fact, the UcD is a really a phase-shift power oscillator and its frequency of operation will be exactly at the point where phase shift through the output filter and other R/C networks back to the comparator is 180 degrees (the inverting hook up of the comparator provides the remaining required 180 degrees - remember, we are simplifying and ignoring any small propagation delay through the comparator and MOSFETs).

It is also revealing to note that the reason the UcD suffers frequency droop at high level outputs is due to the changing phase of the fundamental Fourier component of the highly asymmetrical pulse waveform required to achieve a large "dc" output. As I recall, this waveform "geometry" phase shift approaches 90 degrees in the limit, so at very high output levels, the UcD will naturally operate at a lower frequency to where the additional phase shift through the output filter and feedback circuits is now only 90 degrees (in theory, anyway). With the UcD, oscillation frequency is all about phase.

One of the curious manifestations of this fascinating nonlinear type of circuit is that gain is not continuous with frequency. It "jumps" to different levels at the oscillation frequency (and its harmonics). Looked at from another way, the nonlinear action of saturation at the oscillation frequency acts to suppress gain at non harmonically related frequencies (the lower ones, for all practical class d purposes).

Regards -- analogspiceman

 

[Pafi]

Thanks for this eye opening discussion. Obviously pushing my ideas regarding selfres designs towards topologies with post filter feedback and
LC-feedback-network, in order to get very stable oscilating frequencies. Did you ever try such an arrangement?

You're welcome!

Do you mean you would like to make a steeper phase-characteristics? I don't think it worked. This kind of calculations are good for only to determine idle freq. At high signal-levels the assumptions (ignorance of harmonics) becomes very imprecise. In reality I think a steeper phase-characteristics would cause stronger freq. drop at large input signal.

The solution could be signal-level dependent delay. (Smaller delay at near the rail voltage.) Discrete UcD does something like this inherently!

 

[Pafi]

analogspiceman!

Therefore, at least for small signal perturbations, the sampling portion will always devolve to a zero order hold (or worse).

I disagree. If you have a narrow impulse on PWM input, the output will change (compared to zero input) during the pulse (or never). Not sooner, not later, just during the pulse. No memory (obviously). Think it over! A PW modulator is a comparator! Where is the memory? Nowhere. Then what could hold the signal?

Of course, at sufficiently low frequencies, the sampling process and/or any of its approximations will contribute near zero phase shift.

Near zero? Yes, my Tina simulation shows 1millidegrees of phase-shift at f_triangle/f_sine=10. This is not perfectly zero indeed. (Fourier series made by 65536 points of FFT.)

It is also revealing to note that the reason the UcD suffers frequency droop at high level outputs is due to the changing phase of the fundamental Fourier component of the highly asymmetrical pulse waveform required to achieve a large "dc" output.

I appreciate that you are following your false theory consistently. You assumed that only fundamental component accounts in switching freq, but sadly it's not true. A comparator changes its output exactly when input signal crosses zero, and this almost coincide with the zero crossing of fundamental, but not exactly. You have to take account of all harmonics too, because they becomes dominant at high levels. There is no possibility of simplifications, you have to calculate them one-by-one (and apply transfer function of filters, and inverse fourier transform them), or you could stay at simulation in time-domain.

Phase-shift of fundamental of a PWM signal is monoton function of duty cycle! Eg.: 0 degrees at 50 %, -81 degrees at 95 %, +81 degrees at 5 %. (Sine base-function, t=0 at positive transition.)

If you were right, if phase-change of fundamental would be the reason of freq. change, then it would be antisymmetrical (freq. drop at positive signal, freq. pop at negative signal, or vica-versa). Since we know it's symmetrical, it can not be the reason.

 

[ChocoHolic]

You're welcome!

Do you mean you would like to make a steeper phase-characteristics? I don't think it worked. This kind of calculations are good for only to determine idle freq. At high signal-levels the assumptions (ignorance of harmonics) becomes very imprecise. In reality I think a steeper phase-characteristics would cause stronger freq. drop at large input signal.

The solution could be signal-level dependent delay. (Smaller delay at near the rail voltage.) Discrete UcD does something like this inherently!

Yes, I was thinking about a steeper phase characteristic.
But currently I am absolutely not able to gon into depth with my classD thoughts, because I am completely covered with my normal work and additional an smps design for a friend (fortunately also fitting to my smps needs in my classD project).

Regarding the traditional UcD my brain went on during watching the fireworks yesterday...
The resonance frequency of the output filter is typically one decade below the switching frequency, so it will deliver just marginal less than 180 deg lag phase shift, almost no matter if the switching frequency is moving slightly up or down within normal ranges. From this the self oscillation should run approximately with that frequency at which the lead phase shift of the feedback network equals to the lag phase shift of the delays of comparator+levelshifter+MosFets. Does this fit to your experiences/calculations/simulations?

 

[analogspiceman]

You assumed that only fundamental component accounts in switching freq, but sadly it's not true. A comparator changes its output exactly when input signal crosses zero, and this almost coincide with the zero crossing of fundamental, but not exactly. You have to take account of all harmonics too [...]

When considering operating frequency of an ideal UcD style self-oscillating amplifier at quiescence (no input signal) the first thing to note is that power stage output is a perfect square wave. A square wave is comprised of only odd harmonics all lined up in phase and of strength inversely proportional to harmonic number. When looking at this signal as it makes its way around the loop back to the power stage comparator input, there are several good reasons why these harmonics don't matter much.

First of all, their amplitudes are further reduced (relative to the fundamental) by the number of poles from the output back to the comparator's input (two from the LC filter and perhaps an additional RC right at the comparator). This means that the third harmonic appearing at the comparator will be 30 to 80 times smaller than the fundamental. Additionally, due to the phase alignment, what small amount of harmonics remain won't have any influence on the zero crossing point. Thus, the frequency of oscillation will occur precisely at the point where the phase of the fundamental through the loop is shifted 360 degrees. -- a.s.

 

[luka]

Its all good and everything, but this is not the topic here
To Clock or not to Clock,, should he or not, will it make diffrence in HIS design...

 

[Pafi]

analogspiceman!

You omitted a very important part of my post: "because they becomes dominant at high levels"

I know this calculation is good for idle freq approximation. But you tried to interprete it as explanation of freq drop at high level.

Thus, the frequency of oscillation will occur precisely at the point where the phase of the fundamental through the loop is shifted 360 degrees.

My simulation shows 2 degrees of deviance (between fundamental and real zero-crossings). Freq results: time-base simulation: 357,5 kHz, linearised modell (fundamental component): 370,1 kHz. I wouldn't say "precisely".

luka!

I'm sorry, you are right!

(There are significant differences, but I couldn't say generally one or other would be better.)

 

[kASD]

I vote for Clocked designs

 

[ChocoHolic]

There are valid points in both directions, which I will summarize here.

- Pro self resonant:
a) Typically the self resonant circuits show a lower component count.
b) Strong feedback is very often system immanent up to high frequencies, you get it for free.

-Contra selfres:
a) Many reports about birding. (But I did not hear a birding, when listening to an UcD).
b) Lock up effects.
c) Most designs show massive dropping of the switching frequency at large signals.


- Pro clocked:
a) By principle no beating.
b) In SMPS designs synchronization is often used in order to avoid beating of noise.
c) Digital studio audio equipment usually also is running synchronized, means a clocked and synchronizable power amp is a consequent approach for a homogenous system.
d) Switching frequency does not drop with increasing signals (except carrier aliasing... ).

Contra clocked:
a) Higher component count.
b) Self generated disturbances may cause a jitter, which theoretically might not just generate a frying noise. This jitter and the resulting noise is also being modulated by the music signal and could IMHO also cause something like birding.
c) Strong feedback, especially strong postfilter feedback is a difficult topic even with a PID structured feedback loop. Usually you do not get strong post filter feedback without suffering from carrier aliasing at high signal levels.


I guess this summary does not really help for a decision, but it helps to understand why this discussion is alive since years...