Hi people...
First of all, excuse my english. I'm brazilian, and I don't know english very well...
But, I asked my self a thing about Class D amplifiers: Would a PIC microcontroller and an ADC converter make the work of generating the PWM wave for the mosfets?
I just imagined this, and searched it on the internet, but didn't find anything about...
The only thing I found was the price of an ADC for 16bit and high sample rate... VERY EXPANSIVE!
Do you know any low cost ADC with 16bit and good sample rate?
I hope you help me!
=)
thanks!
First of all, excuse my english. I'm brazilian, and I don't know english very well...
But, I asked my self a thing about Class D amplifiers: Would a PIC microcontroller and an ADC converter make the work of generating the PWM wave for the mosfets?
I just imagined this, and searched it on the internet, but didn't find anything about...
The only thing I found was the price of an ADC for 16bit and high sample rate... VERY EXPANSIVE!
Do you know any low cost ADC with 16bit and good sample rate?
I hope you help me!
=)
thanks!
Yes, a PIC microcontroller and an ADC would work in creating PWM for Class D amplifiers but, designing it to work properly would be very hard to achieve. Considering the complexity of Class D amplifiers, it would take you months or maybe years to finished it with that kind of approach.
If you are concerned of the price, try obtaining free samples from semiconductor companies like Texas Instruments. They have chips that are designed for Class D amplifications for audio.
If you are concerned of the price, try obtaining free samples from semiconductor companies like Texas Instruments. They have chips that are designed for Class D amplifications for audio.
Hi jocthbr!
PIC is c r a p for this purpose. It can multiply very slowly and the clock frequency is also low-end. You can't make a good resolution PWM. And You will get to nowhere in quality with UPWM.
Try using FPGA. You don't have to learn any instruction set or something like that. You should only know digital logic and digital signal processing, so you should only know what you want to do. For example Xilinx enabled to download free evaluation version of Xilinx System Generator for DSP, what is a MATLAB Simulink-based tool for FPGA signal processing. You can make your hardware from blocks down to logic elements. You can do anything with that. Then you can simulate your design bitwise with Simulink. Simulate your filters and control loops exatly, make any nonlinear model of the analog environment, make FFT or whatever you want. Then the whole design is compilable to your FPGA board and uploadable through JTAG. For example a Xilinx XC3S400 contains 16 pieces of 18x18 bit ~5ns cycle time multipliers, ~7168 registered configurable logic, 36 kbytes of zero-latency SRAM, four high-frequency PLLs, huge number of I/O ports. For example signal processing with this basic one is possible up to ~100 MHz clock assuming <= 64 bit word-length adders between two register-fields. For audio frequency range you can make 2048-tap 18-bit coefficient FIR filter with only one multiplier unit, or 16 pieces of 128-tap or etc. I think even 10000 PIC couldn't do what this can if all units would be utilized. And it's only a single basic FPGA IC for a few $s.
Regards,
Gyula
PIC is c r a p for this purpose. It can multiply very slowly and the clock frequency is also low-end. You can't make a good resolution PWM. And You will get to nowhere in quality with UPWM.
Try using FPGA. You don't have to learn any instruction set or something like that. You should only know digital logic and digital signal processing, so you should only know what you want to do. For example Xilinx enabled to download free evaluation version of Xilinx System Generator for DSP, what is a MATLAB Simulink-based tool for FPGA signal processing. You can make your hardware from blocks down to logic elements. You can do anything with that. Then you can simulate your design bitwise with Simulink. Simulate your filters and control loops exatly, make any nonlinear model of the analog environment, make FFT or whatever you want. Then the whole design is compilable to your FPGA board and uploadable through JTAG. For example a Xilinx XC3S400 contains 16 pieces of 18x18 bit ~5ns cycle time multipliers, ~7168 registered configurable logic, 36 kbytes of zero-latency SRAM, four high-frequency PLLs, huge number of I/O ports. For example signal processing with this basic one is possible up to ~100 MHz clock assuming <= 64 bit word-length adders between two register-fields. For audio frequency range you can make 2048-tap 18-bit coefficient FIR filter with only one multiplier unit, or 16 pieces of 128-tap or etc. I think even 10000 PIC couldn't do what this can if all units would be utilized. And it's only a single basic FPGA IC for a few $s.
Regards,
Gyula
yeah...
it makes the question go harder..
I could use a FPGA, but I don't have any knowledge about them...
I'm not looking for a high-end Class D amplifier...
For me, it's enough a low-frequency (like 10 to 2000hz) class d amplifier...
Do you know any other efficient way to make a simple class d amplifier?
it makes the question go harder..
I could use a FPGA, but I don't have any knowledge about them...
I'm not looking for a high-end Class D amplifier...
For me, it's enough a low-frequency (like 10 to 2000hz) class d amplifier...
Do you know any other efficient way to make a simple class d amplifier?
Maybe other diyer's have more experience about analog Class-D than me. I have already done only analog switching-mode PSUs but not switching-mode amps. Eva and Fredos are very skilled on that field. Maybe they are the brightest on this forum. They have much more experience about analog switching-mode instruments than me.
Gyula
Gyula
Hi darkfenriz!
I made my thesis about a fed-back Class-D amplifier. It utilized a 2-DOF controller embedded in Smith-Predictor structure. The control loop also contained feedforward Power Supply voltage compensation and drove a linerized and noise-shaped PWM modulator. The main innovation was in the feedback which cancelled the transposed carrier sidebands in the audible range.
The input ADC was a PCM4202. The output and PSV ADCs were two ADS8422s driven with OPA1632s. It had lower distrortion with feedback than open-loop.
There were 2 pieces of 2x FIR interpolators from the 99MHz/1024 input sample rate to the 99MHz/256 PWM carrier. There was also a 256x CIC interpolator for the PWM linearization. Later I wondered about phase-linearization of the fed-back system with the interpolator filters but I haven't do that because lack of time.
A short P.S. to jocthbr:
I made an analog-input based digital Class-D amp like you are planning to do few years ago, not with PIC but with Flash-converter and counters. The main problem for these low word-length PWMs comes from the quantization. Which happens at the input ADC and the output PWM as well. For low-frequency or low-amplitude audio signals the signal will remain in the same quantization step for two or more samples. Let's make a simple modelling of the quantization with adding an error signal to the unquantized audio. Then the error signal is the difference between the exact input and the derived quantization level. Consider this you can see the error signal is wrapped to the quantization step range, and when the audio signal reaches the next quantization level it falls to zero. If the audio signal remains in the same quantization step range for more than one samples the randomization effect between the sample values caused by the wrapping will not happen and the samples will be deterministic (correlated), will depend on the input signal. This causes the noise spectra become lined and means there are high energy frequencies what relates to periodic components in the time-domain. Periodic noise is very well audible and can be annoying as well. This means that you will always hear hissing with low-frequency or low-amplitude input. In order to cancel this effect after the input ADC you should do dithering what I don't want to describe now, but I will if you want me to do. At the PWM modulator for the cancellation you should apply noise-shaping which means feed back of the difference of unquantized and quantized audio signal to the PWM input through a simple filter. Assuming good linearity for the PWM the quantized audio signal is simple to make with trucation to the PWM word length. And the difference of original and the truncated signal will represent the added error signal multiplied by -1 in the former linear model of additive noise. Expand this model with a few taps of delayed error values and you will get the noise-shaper filter with the first tap fixed to -1 value. Now the model with the filter not only adds an error signal to the audio but adds a filtered error signal to that. You can set the noise spectra with the taps' coefficient set amplitude characteristic of this noise-shaper filter. For real zeros on the unit circle of z-domain the tap coefficients have to be integer values what makes the multiplications reduceable to a few bit-shift and add operation even if those are not integer power of 2. The zeros should be set to the audible range what is around z=1 and maybe few of them are practical to be set to Fs/2 in order to reduce the noise power of high-order noise-shaper filters. The price of the fixed first coefficient is the largest deal with the noise shaping and it comes from the impulse energy of the filter is always greater than 1 because of the integer coefficients greater than or equal to 1 in absolute value. This means the filter always enlarges the noise power apart from the good attenuation around z=1 what is a benefit in at about the f<=Fs/20 range. This causes Fs/20 should be higher than the audible frequency range and you can only hope your speakers are linear enough not to transpose the higher frequency noise components to the audible range. Or you have to use steep, high-order demodulation filter after the PWM in order to attenuate the noise power in the audible range, and this filter will also have large phase-shift. You have to consider if a PIC can do it or not. I think it's on the edge of it's capability because of the possible high Fs and word length larger than 8-bit. And it does almost nothing with this task. There's no feedback with regulator, no linearizer for the PWM, no volume control. It can do almost nothing. Only a litter of somehow PWMed something.
So I think a simple analog Class-D can perform much more better.
I made my thesis about a fed-back Class-D amplifier. It utilized a 2-DOF controller embedded in Smith-Predictor structure. The control loop also contained feedforward Power Supply voltage compensation and drove a linerized and noise-shaped PWM modulator. The main innovation was in the feedback which cancelled the transposed carrier sidebands in the audible range.
The input ADC was a PCM4202. The output and PSV ADCs were two ADS8422s driven with OPA1632s. It had lower distrortion with feedback than open-loop.
There were 2 pieces of 2x FIR interpolators from the 99MHz/1024 input sample rate to the 99MHz/256 PWM carrier. There was also a 256x CIC interpolator for the PWM linearization. Later I wondered about phase-linearization of the fed-back system with the interpolator filters but I haven't do that because lack of time.
A short P.S. to jocthbr:
I made an analog-input based digital Class-D amp like you are planning to do few years ago, not with PIC but with Flash-converter and counters. The main problem for these low word-length PWMs comes from the quantization. Which happens at the input ADC and the output PWM as well. For low-frequency or low-amplitude audio signals the signal will remain in the same quantization step for two or more samples. Let's make a simple modelling of the quantization with adding an error signal to the unquantized audio. Then the error signal is the difference between the exact input and the derived quantization level. Consider this you can see the error signal is wrapped to the quantization step range, and when the audio signal reaches the next quantization level it falls to zero. If the audio signal remains in the same quantization step range for more than one samples the randomization effect between the sample values caused by the wrapping will not happen and the samples will be deterministic (correlated), will depend on the input signal. This causes the noise spectra become lined and means there are high energy frequencies what relates to periodic components in the time-domain. Periodic noise is very well audible and can be annoying as well. This means that you will always hear hissing with low-frequency or low-amplitude input. In order to cancel this effect after the input ADC you should do dithering what I don't want to describe now, but I will if you want me to do. At the PWM modulator for the cancellation you should apply noise-shaping which means feed back of the difference of unquantized and quantized audio signal to the PWM input through a simple filter. Assuming good linearity for the PWM the quantized audio signal is simple to make with trucation to the PWM word length. And the difference of original and the truncated signal will represent the added error signal multiplied by -1 in the former linear model of additive noise. Expand this model with a few taps of delayed error values and you will get the noise-shaper filter with the first tap fixed to -1 value. Now the model with the filter not only adds an error signal to the audio but adds a filtered error signal to that. You can set the noise spectra with the taps' coefficient set amplitude characteristic of this noise-shaper filter. For real zeros on the unit circle of z-domain the tap coefficients have to be integer values what makes the multiplications reduceable to a few bit-shift and add operation even if those are not integer power of 2. The zeros should be set to the audible range what is around z=1 and maybe few of them are practical to be set to Fs/2 in order to reduce the noise power of high-order noise-shaper filters. The price of the fixed first coefficient is the largest deal with the noise shaping and it comes from the impulse energy of the filter is always greater than 1 because of the integer coefficients greater than or equal to 1 in absolute value. This means the filter always enlarges the noise power apart from the good attenuation around z=1 what is a benefit in at about the f<=Fs/20 range. This causes Fs/20 should be higher than the audible frequency range and you can only hope your speakers are linear enough not to transpose the higher frequency noise components to the audible range. Or you have to use steep, high-order demodulation filter after the PWM in order to attenuate the noise power in the audible range, and this filter will also have large phase-shift. You have to consider if a PIC can do it or not. I think it's on the edge of it's capability because of the possible high Fs and word length larger than 8-bit. And it does almost nothing with this task. There's no feedback with regulator, no linearizer for the PWM, no volume control. It can do almost nothing. Only a litter of somehow PWMed something.
So I think a simple analog Class-D can perform much more better.
The output feedback was from the output of the demodulation filter, directly from the output terminals. The PSV feedforward measured the power supply voltage directly. Of course there were many feedback loops in the FPGA signal processing as well. For example in the Smith-Predictor and Noise Shaper. And in every integrator of the CIC filters, and inside the DCMs and even in the 2-DOF controller filter... ...and outside of it every op. apm. were fed-back on the board 
.
It was also stable unoaded.
The utilization of the XC3S400 FPGA was about 96 % of Slices and 16 pieces of dedicated multipliers and worked with 99 MHz clock frequency. The signal processing was 36-bit wide up to the Noise Shaper. We originally built a simpler one with György Dancsi for the SSC last year autumn. I used the FIR interpolators from that what Gyuri made, and the 2-DOF controller, and developed new blocks with the written thesis in 2.5 weeks. That was a very hard deadline. I made that on Géza Balázs and Tibor Kimpián's FPGA board what they made for a loudspeaker cone velocity feedback amplifier project for the SSC in 2005. At this time it's in the Acoustical Laboratory of Building I.
The board contains one more ADS8422. We are planning to expand the control with cone velocity feedback for this amp as well.
P.S.: I forgot to mention that there's a mistake in Post #9. Not the absolute sum of the NS filter's coefficients represents the power gain but the squared sum, according to the Parseval-theorem. But it doesn't matter for the understanding because the square and the absolute value of first coefficient are always equal to 1. So the sum will always be larger than 1.
.It was also stable unoaded.
The utilization of the XC3S400 FPGA was about 96 % of Slices and 16 pieces of dedicated multipliers and worked with 99 MHz clock frequency. The signal processing was 36-bit wide up to the Noise Shaper. We originally built a simpler one with György Dancsi for the SSC last year autumn. I used the FIR interpolators from that what Gyuri made, and the 2-DOF controller, and developed new blocks with the written thesis in 2.5 weeks. That was a very hard deadline.
I made that on Géza Balázs and Tibor Kimpián's FPGA board what they made for a loudspeaker cone velocity feedback amplifier project for the SSC in 2005. At this time it's in the Acoustical Laboratory of Building I.The board contains one more ADS8422. We are planning to expand the control with cone velocity feedback for this amp as well.
P.S.: I forgot to mention that there's a mistake in Post #9. Not the absolute sum of the NS filter's coefficients represents the power gain but the squared sum, according to the Parseval-theorem. But it doesn't matter for the understanding because the square and the absolute value of first coefficient are always equal to 1. So the sum will always be larger than 1.
- Status
- This old topic is closed. If you want to reopen this topic, contact a moderator using the "Report Post" button.