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Old 20th April 2008, 05:08 PM   #21
TheMG is offline TheMG  Canada
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Quote:
Originally posted by zilog


I have thought about upgrading myself to some kind of DSO, what are the pros and cons when it comes to class d and smps?

Sometimes it can be easier to see issues such as overshoot on an analog scope. Nearly all DSOs employ some form of averaging, which can make overshoot appear non-existent. On many DSOs you can turn averaging off but sometimes that isn't quite enough due to the sample rate and other factor.

High quality (expensive) DSOs will be better at capturing this kind of stuff, but the less expensive kind might not be able to.
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Old 25th April 2008, 07:51 PM   #22
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why not use infinite persistence on DSO? That should capture overshoot. Some color scopes will change the colors as the number of 'hits' in a certain area occur. That gives you some statistical feel for where the overshoot occurs most of the time.

There was just an article in EDN (tales from the cube) where they debugged using analog scope, waited until it was dark out, turned off the lights, cranked up the scope intensity, and kept watching the trace looking for failures. Fun, eh?
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Old 28th April 2008, 09:57 AM   #23
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OK, I am back to experimenting.
I fed the dead time/IR2110/switching mosfets stage from a generator.

The problem is get very high switching losses, current consumption at 200kHz no load is around 130mA. Overshooting is low, around 5%.

Please help me and tell me what is the problem:

- dead time is around 120ns, should I increase it?

-MOSFETS are cheap and dirty STP22NE10L, not that bad in term of Qrr and Qgd, but the bad thing is low Vgs-th. Are they really not suitable for class D amp?

- I have no mosfet snubbers, could a RC from drain to source help? If so what should be the starting RC values?

Best regards
Adam
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Old 7th August 2008, 09:05 PM   #24
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After yet another "dead time" in my experimenting with this amp I went back.

I've noticed a strange thing, probably I've killed something:

The signal on the output is (more or less) typical switching waveform, but after around 30 seconds or so current consumption starts to rise quickly and finaly the bootstrap- charging diode 1n4007 at IR2110 smokes.

Experts, please give me a tip on what could be dead: capacitor (tried 220uF, 47uF, same results), upper side mosfet, driver, ...?

Thanks in advance!

Adam
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Old 8th August 2008, 02:11 PM   #25
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continued.

I swapped ferrite beads at gates with 18R, now MOSFETs cross-conduct like silly, idle consumption around 250mA or so, rising with time. Are logic-level MOSFETs reall so damn unsuitable for class-D half bridge?
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Old 8th August 2008, 03:11 PM   #26
Eva is offline Eva  Spain
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I have never worked with logic level MOSFET but they are likely to require some negative bias at turn off (ferrite bead on gate and slight resonance) and some delay at turn on. A low gate supply voltage like 10V should work better as it results in faster turn-off. Gate resistors result on poor switching performance, adding an inductive component results in a 2nd order system with more square-wave like gate waveforms. Then series resistance can provide the right amount of damping.

You have to ensure that proper switching timing is always taking place, not only when the amplifier is idle but at all duty cycles and particularly near the rails, where pulses become narrower, noise margin smaller and comparator bouncing may arise resulting in unexpected disasters. You may find useful to get the trigger signal to the oscilloscope from the output of the comparator (if it isn't too weak).
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Old 8th August 2008, 03:49 PM   #27
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Hi, Darkfenriz,

I found the datasheet of UCC27200 and MP7720 has some important points for PCB layout. Like page 22 from UCC27200 datasheet.
The tracks from driver IC to mosfet gate and it's return path (mosfet source) to the IC should be short and wide (>1.5mm if possible). The position of bootstrapp C and supply C should be as close as possible to the IC. Input+feedback components connected to +in and -in of the main comparator should be as close as possible to the pins.
Another good paper is AN1135 from IR.
You use many logic gates in series? I found that to get better sound, the propagation delay (open loop) should be as minimal as possible, mean advoid too many logic gates when possible, cause each gate has quite some delay.
I tried many permutation with 2 side PCB. My conclusion is that a proper PCB layout need at least 4 layer. Cannot do it perfectly with only 2 layer.
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