Sure...except that there is no connection to the non-inverting input of the OTA on the IRS2092.
Exactly...so how did you connect the post-filter feedback to the non-inverting input of the OTA as shown in post #10?
I am connecting the input to inverting pin of OTA configured as inverting buffer. If you look at datasheet of IRS2092, its internal comparator is also inverting. Therefore its ok to connect that way.
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I've a question about this idea.
The OTA is now connected in an inverting way.
With a normal amplifier the circuit wouldn't work because the whole is made non-inverting I think? (because the comparetar is also inverting)
Can someone explain how this works with OTA's?
I don't have so many experience with OTA circuits/theory.
The OTA is now connected in an inverting way.
With a normal amplifier the circuit wouldn't work because the whole is made non-inverting I think? (because the comparetar is also inverting)
Can someone explain how this works with OTA's?
I don't have so many experience with OTA circuits/theory.
This circuit squelches OTA gain to obtain stability. In my frequency domain sims the result's quite low loop gain for the amp. However, in the time domain I get incorrect comparator behavior from LTSpice with several different modeling techniques. Haven't had a chance to get that sorted so I don't have proper confirmation of the performance. Perhaps Kanwar's measured THD+N on his build.
OK, but can you maybe tell me something about the theory itself?
I can't find any usable data/information so far.
Besides, I tried the little circuit on post 48, it worked BUT it gave me a huge offset on the output of the amplifier (-9Vdc)
At the end I had nice bright fireworks (unfortunately no champagne)
This was tested on a IRAUDAMP9 like amplifier (with a totally different 4 layer PCB).
When I started, I discovered that there was a asymmetrical square wave (duty cycle wasn't 50% at all!). After switching of and on, this somehow changed.
The ferite in seires with the voltage rail broke and the Vee pin of the lower MOSFET
(and a bunch of other parts after that).
I can't find any usable data/information so far.
Besides, I tried the little circuit on post 48, it worked BUT it gave me a huge offset on the output of the amplifier (-9Vdc)
At the end I had nice bright fireworks (unfortunately no champagne)
This was tested on a IRAUDAMP9 like amplifier (with a totally different 4 layer PCB).
When I started, I discovered that there was a asymmetrical square wave (duty cycle wasn't 50% at all!). After switching of and on, this somehow changed.
The ferite in seires with the voltage rail broke and the Vee pin of the lower MOSFET
(and a bunch of other parts after that).
The data sheet of the IRS2092 is misleading.
When you measure from COMP towards HO you will find a non inverting behavior.
However I would not dare to say that the data sheet is really wrong, could be just sort of incomplete. The flippy behavior of the comparator could fit to an inverting comparator as shown in the data sheet - and one of the following stages inverting once more.
Anyhow, for basic understanding of the IRS2092 it is sufficient to know that the path from COMP to HO is non inverting.
Mmm, bridge drivers have complimentary gate outputs pretty much by definition. Figure 1 on page 11 of the IRF2092 datasheet is quite specific about LO being inverted with respect to COMP. I suppose it might be helpful if the simplified block diagram included a circle on the HO path to indicate the inversion with respect to the comparator's negative input. But, well, it is a simplified diagram. And its lack of specificity in regards to polarity and the need to look elsewhere for that information hopefully fairly obvious.
b_force, you might look at Bruno Putzey's AES papers on UcD and nCore and Tim Green's series on op amp stability. An error amplifier in class D performs the same role as the control amplifier in a composite amplifier.
b_force, you might look at Bruno Putzey's AES papers on UcD and nCore and Tim Green's series on op amp stability. An error amplifier in class D performs the same role as the control amplifier in a composite amplifier.
Yup, the data sheet from Oct 2013 also shows the non inverting signal HO in the same graph.
The simplified schematic is misleading, but the timing figures are fine.
Yeah, in my opinion the datasheets and application notes are very minimalistic.
They don't go into very big details, so a lot has to be done by trial and error (beside the mistakes,incompleteness and errors here and there)
I'm familiar with Bruno's papers, but haven't heart of Tim Green.
Is there a nice link where I can get his work all together? (I only find lose bits and pieces)
Btw, wouldn't it be possible to invert the outputs of the driver again to make a bridged amplifier with only one "MOSFET driver"?
They don't go into very big details, so a lot has to be done by trial and error (beside the mistakes,incompleteness and errors here and there)
I'm familiar with Bruno's papers, but haven't heart of Tim Green.
Is there a nice link where I can get his work all together? (I only find lose bits and pieces)
Btw, wouldn't it be possible to invert the outputs of the driver again to make a bridged amplifier with only one "MOSFET driver"?
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