Thanks rumors. Is there a reason why your schematic does not follow the equivalent schematic of the datasheet? Anyway, I was always wondering what values those constant current sources would approximately have and your schematic allowed me to complete my SPICE model for SwitcherCAD III (LTspice). Note: This model does not follow schematic presented by rumors but the schematic presented by the datasheet.
The quick test shows that this model at least gives pretty decent results. Note that protection schemes are not modelled here. Seems like the next step is to dwelve into reading the AN-898...
.SUBCKT LM3886 posin negin out posrail negrail mute
* IN+ IN- OUT VCC VEE MUTE
*
Q1 posrail posin N004 0 NPN
I1 N004 negrail 0.25m
Q2 posrail negin N003 0 NPN
I2 N003 negrail 0.25m
Q3 N011 N003 N010 0 PNP
Q4 N011 N018 N012 0 NPN
R1 N012 negrail 2.2k
I3 N018 negrail 0.1m
Q5 N017 N018 N024 0 NPN
R2 N024 negrail 2.2k
Q6 posrail N011 N018 0 NPN
R3 N009 N010 1.1k
R4 N009 N023 1.1k
Q7 N017 N004 N023 0 PNP
Q8 N017 N013 N016 0 PNP
Q9 N011 N025 N019 0 PNP
R5 N015 N016 4.7k
R6 N015 N019 4.7k
R7 N013 gndpin 10k
D1 N025 gndpin D
D2 gndpin N025 D
R8 out N025 10k
C1 out N017 10p
I4 N026 negrail 1m
Q10 posrail N017 N026 0 NPN
Q11 N030 N026 N031 0 NPN
R9 N031 negrail 800
Q12 N009 N008 N014 0 PNP
Q13 N015 N022 N014 0 PNP
I5 posrail N014 1m
I6 N022 negrail 1m
D3 N021 N022 D
D4 N020 N021 D
R10 posrail N020 1k
D5 N007 N008 D
D6 N006 N007 D
R11 posrail N006 1k
Q14 N008 gndpin N005 0 NPN
R12 N005 N001 1k
D7 N002 mute D
D8 N001 N002 D
D9 N032 N031 D
R13 N034 negrail 150
Q15 out N032 N034 0 NPN
Q16 out N034 N036 0 NPN
R14 N036 negrail 0.45
Q17 N032 N030 out 0 PNP
D10 N029 N030 D
D11 N028 N029 D
D12 N027 N028 D
R15 N033 out 150
Q18 posrail N027 N033 0 NPN
Q19 posrail N033 N035 0 NPN
R16 N035 out 0.45
I7 posrail N027 2.5m
.model D D
.model NPN NPN
.model PNP PNP
.end lm3886
The quick test shows that this model at least gives pretty decent results. Note that protection schemes are not modelled here. Seems like the next step is to dwelve into reading the AN-898...
.SUBCKT LM3886 posin negin out posrail negrail mute
* IN+ IN- OUT VCC VEE MUTE
*
Q1 posrail posin N004 0 NPN
I1 N004 negrail 0.25m
Q2 posrail negin N003 0 NPN
I2 N003 negrail 0.25m
Q3 N011 N003 N010 0 PNP
Q4 N011 N018 N012 0 NPN
R1 N012 negrail 2.2k
I3 N018 negrail 0.1m
Q5 N017 N018 N024 0 NPN
R2 N024 negrail 2.2k
Q6 posrail N011 N018 0 NPN
R3 N009 N010 1.1k
R4 N009 N023 1.1k
Q7 N017 N004 N023 0 PNP
Q8 N017 N013 N016 0 PNP
Q9 N011 N025 N019 0 PNP
R5 N015 N016 4.7k
R6 N015 N019 4.7k
R7 N013 gndpin 10k
D1 N025 gndpin D
D2 gndpin N025 D
R8 out N025 10k
C1 out N017 10p
I4 N026 negrail 1m
Q10 posrail N017 N026 0 NPN
Q11 N030 N026 N031 0 NPN
R9 N031 negrail 800
Q12 N009 N008 N014 0 PNP
Q13 N015 N022 N014 0 PNP
I5 posrail N014 1m
I6 N022 negrail 1m
D3 N021 N022 D
D4 N020 N021 D
R10 posrail N020 1k
D5 N007 N008 D
D6 N006 N007 D
R11 posrail N006 1k
Q14 N008 gndpin N005 0 NPN
R12 N005 N001 1k
D7 N002 mute D
D8 N001 N002 D
D9 N032 N031 D
R13 N034 negrail 150
Q15 out N032 N034 0 NPN
Q16 out N034 N036 0 NPN
R14 N036 negrail 0.45
Q17 N032 N030 out 0 PNP
D10 N029 N030 D
D11 N028 N029 D
D12 N027 N028 D
R15 N033 out 150
Q18 posrail N027 N033 0 NPN
Q19 posrail N033 N035 0 NPN
R16 N035 out 0.45
I7 posrail N027 2.5m
.model D D
.model NPN NPN
.model PNP PNP
.end lm3886
Whoops, missed the common pin. The correct syntax is
.SUBCKT LM3886 posin negin out posrail negrail mute gndpin
.SUBCKT LM3886 posin negin out posrail negrail mute gndpin
teemuk,
Have you allowed for the area (on the die) of the output transistors being much larger than the others? Also you appear to have default transistor parameters rather than real devices. At the moment the modelled device will appear better/different to the real device.
A macro model is the opposite of what you have i.e current sources etc are put together to represent the performance of the device, not the real circuit.
See this for a macro model of an op-amp:
http://www.ecircuitcenter.com/Circuits/opmodel1/opmodel1.htm
Have you allowed for the area (on the die) of the output transistors being much larger than the others? Also you appear to have default transistor parameters rather than real devices. At the moment the modelled device will appear better/different to the real device.
A macro model is the opposite of what you have i.e current sources etc are put together to represent the performance of the device, not the real circuit.
See this for a macro model of an op-amp:
http://www.ecircuitcenter.com/Circuits/opmodel1/opmodel1.htm
consort_ee_um said:
I guess you answered the question yourself. Yes, the transistors use default parameters. I'm not that experienced in building spice models that I could model each transistor individually.
Definitely. What model would not? The real question is how and how much. I would not claim that this model is even closely accurate but IMO, it gives decent results in basic sims and compared to Gerry's model (which BTW is the only other model of LM3886 besides this one I'm aware of) I'd say this one behaves a lot more realistically. This is at least enough for me.
There are obvious problems in the model that show up when the circuit clips too much (this can be revealed in the sim) and I'm sure the model also has a broader bandwidth than the actual device as junction capacitances are ignored in default transistor parameters.
The model could definitely be made better by replacing the internal constant current source elements with discrete CCS circuits and by modeling the transistor parameters. Also, as noted, the model circuit also lacks VI-limiter, over-and undervoltage protection plus SPiKe protection - which have huge impact on the chips clipping behaviour. This model does not replicate them. Currently I have other priorities than working on improving this model so if I may suggest, enjoy it as it is and realize it´s limitations and shortcomings.
Warning: the current generators are invent to you and adapt you to my simulation with the microcap, simulation that close to the real behavior of 3886, but all the reliable one (the protections do not lack, do not know the real parameters of the transistors within the chip)
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Quite a few typo's - I think I've caught them although I don't know if the model works properly. I think you have to tie MUTE to the -ve rail via a 10k resistor.
.SUBCKT LM3886 posin negin out posrail negrail mute gndpin
* IN+ IN- OUT VCC VEE MUTE GND
*
* LM3886 spice model by teemuk 21032007 ver.1b
Q1 posrail posin N004 0 NPN
I1 N004 negrail 0.25m
Q2 posrail negin N003 0 NPN
I2 N003 negrail 0.25m
Q3 N011 N003 N010 0 PNP
Q4 N011 N018 N012 0 NPN
R1 N012 negrail 2.2k
I3 N018 negrail 0.1m
Q5 N017 N018 N024 0 NPN
R2 N024 negrail 2.2k
Q6 posrail N011 N018 0 NPN
R3 N009 N010 1.1k
R4 N009 N023 1.1k
Q7 N017 N004 N023 0 PNP
Q8 N017 N013 N016 0 PNP
Q9 N011 N025 N019 0 PNP
R5 N015 N016 4.7k
R6 N015 N019 4.7k
R7 N013 gndpin 10k
D1 N025 gndpin D
D2 gndpin N025 D
R8 out N025 10k
C1 out N017 10p
I4 N026 negrail 1m
Q10 posrail N017 N026 0 NPN
Q11 N030 N026 N031 0 NPN
R9 N031 negrail 800
Q12 N009 N008 N014 0 PNP
Q13 N015 N022 N014 0 PNP
I5 posrail N014 1m
I6 N022 negrail 1m
D3 N021 N022 D
D4 N020 N021 D
R10 posrail N020 1k
D5 N007 N008 D
D6 N006 N007 D
R11 posrail N006 1k
Q14 N008 gndpin N005 0 NPN
R12 N005 N001 1k
D7 N002 mute D
D8 N001 N002 D
D9 N032 N031 D
R13 N034 negrail 150
Q15 out N032 N034 0 NPN
Q16 out N034 N036 0 NPN
R14 N036 negrail 0.45
Q17 N032 N030 out 0 PNP
D10 N029 N030 D
D11 N028 N029 D
D12 N027 N028 D
R15 N033 out 150
Q18 posrail N027 N033 0 NPN
Q19 posrail N033 N035 0 NPN
R16 N035 out 0.45
I7 posrail N027 2.5m
.model D D
.model NPN NPN
.model PNP PNP
.end lm3886
[remove the '.txt' from the symbol filename]
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