T-network: the better feedback solution?

[theChris]

i've built one of these amps last year. i had a post about it but no pics. i called it the HI3GC -- high input impedance inverting gainclone.

used as a woofer amp.

pros to design:
1.) small feedback cap.
2.) stable, it worked fine.

cons:
1.) increased DC offset (70mV for what should be equal input biases). this was on a bridged design, but the dc offset was overall higher then the non-HI3GC
2.) more parts
3.) you can get more dependence on tolerances.

this was on a lm4780, so i'd suspect chip difference should have been low...

[carlosfm]

Originally posted by theChris
this was on a lm4780, so i'd suspect chip difference should have been low...

The difference in DC-offset between the two channels of this chip is very low.
After all, it's a 2-channel chip.
But the resulting DC-offset still varies from chip to chip.

[carlosfm]

Originally posted by Joe Rasmussen
...so other WILL convert to T-Network. [/B]

I will try it.
With valve buffer.

[Joe Rasmussen]

Originally posted by Pedja

Hello Joe,

....This practically means that the initial offset after the first resistor is amplified by the factor of 101.

Pedja

Yes indeed, it seems that changing this ratio is desirable, to say around 50:1 or even a little lower, like 46:1. I am going to try the following:

If retaining that 10K but increasing 100R to 220R (staying with standard values), now increase the other 10K to 22K, retain the 22K input Z (or similarly 18K + 4K7 with the standard tube buffer with LPF), then 22K on (+) input to ground. This should pretty much halve the potential DC Offset so that rarely should go higher than 25mV? Should work.

This will remove further any need to null, and besides nulling is not desirable in Terry's view and I'm coming around to that view as well. For other DIY'ourselfers who wish to assemble this, or update their amps to T-Network, we need to guide them and give them a set of fixed values that works.

So my revised suggestion is, 22K input Z, then 22K to 220R which is grounded, then to 10K to output, Matching 22K on (+) is 1% near ideal target 22K2. Gain is in the mid-fourties.

The ideal 22K2 results from 10K/220R in parallel = 218R plus 22K in series = 22K2 rounded.

This will balance both 'R' and 'C' and reasonably low DC Offset.

I will also post a revised schematic so the above will be clearer for everyone.

Joe R.

[Joe Rasmussen]

Yikes!

That didn't work out, went from +38mV to +52mV - back to the drawing board - in the meantime stay with earlier values.

[theChris]

Originally posted by carlosfm


The difference in DC-offset between the two channels of this chip is very low.
After all, it's a 2-channel chip.
But the resulting DC-offset still varies from chip to chip.

i meant that the DC offset couldn't be easily attributed to "chip to chip" issues becuase the chips were integrated together. i know 1 channel had 20mV alone, and combined it came to 70mV...

i'mm have to go home and find out what resistors i used. i think there was a 330 ohm in there somewhere. i remeber the values all lines up fairly well.

[Nuuk]

He also feels that since R and C (or DC and AC) Z paths are more important and should both be the same, so live with the Offset of less than 50mV, don't null the DC. So it may well sound better if left un-nulled.

I have always found (and reported) with the IGC (using a single feedback resistor), that it sounds better to me when I accept the DC offset not being zero and don't try and null it with the resistor from non-inverting to ground.

The best sounding IGC I have has DC offset of around 50mV on one channel and around 30mV on the other.

Full marks to Joe for trying to make this available to those of us without the technical understanding, a policy that I have always tried to adhere to with Decibel Dungeon. I for one, greatly appreciate his attitude!

"IT IS THE FRUIT THAT MAKES THE TREE BOW LOW."

[Joe Rasmussen]

OK, while many of our Euro Brethren still have their heads on pillows, I have been a busy bee.

I now know why the last one blew out from 38mV to 52mV. This particular chip has significant more Input Offset current - so increasing to 22K that became the dominant factor.

Let's examine four different chips:

One:

(+) Input Current = 0.105uA

(-) Input Current = 0.150uA

Input Offset Current = 0.045uA **** very high - not within spec

Input Offset Voltage = 3.1mV **** not typical

DC Offset = 38mV


Two:

(+) Input Current = 0.080uA

(-) Input Current = 0.072uA

Input Offset Current = 0.008uA **** very good

Input Offset Voltage = 0.1mV

DC Offset = 8mV


Three:

(+) Input Current = 0.080uA

(-) Input Current = 0.080uA

Input Offset Current = zero **** perfect

Input Offset Voltage = 0.1mV

DC Offset = 6mV


Four:

(+) Input Current = 0.100uA

(-) Input Current = 0.080uA

Input Offset Current = 0.020uA

Input Offset Voltage = 0.5mV

DC Offset = 26mV

Look at the data sheeet One is not within spec on Input Offset current, and 3.1mV Offset voltage is not typical (1mV) but within max (10mV). I say this because I believe One is not typical overall.

All above vere 10K/100R/10K & 10K on (+).

Now changing this to 22K/220R/10K (on output) & 22K on (+), got the following result:

One: Went up from 38mV to 52mV - affected by Input Offset Current and voltage - but more suspicion re current.

Two: Went down from 8mV to 4mV - the reduction because Offset current is low. So is Offset voltage.

So using 10K/100R/10K & 10K on (+), is better able to deal with Input Offset current. Whereas 22K/220R/10K (on output) & 22K reduces DC Offset on the main output only if Input Offset current is reasonable or typical.

There there is a point where going for better than 100:1 ratio down to 46:1 ratio ought to be better and usually is, but in the, hopefully only occasional chip, the imbalance in the input currents swamps the advantage because we end up using 22K - the higher Z becomes a disadvantage.

WHEW!

Wake up guys... awaiting feedback.

Joe R.

[Joe Rasmussen]

Originally posted by Nuuk


Full marks to Joe...

Hey Nick, I will make you president of my fan club...

Seriously, while I think of it, I also want to thank Terry Demol for picking his brains.

Joe R.

[Nuuk]

I'm awake and listening Joe (I am still partly on Laverton time despite the 24 year gap ).

For a newbie, how do you measure the chip to see if it is within spec? Is it as simple as placing a meter in series with each input and reading the current?