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Old 20th July 2004, 02:23 PM   #11
GregGC is offline GregGC  Canada
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To get a better DC output offset you need to have R19=R4||(R10+R7) and R20=R5||(R11+R8).

Why didn't you use Non iverting topologie? It'll solve the low impedance voltage much easier.

/Greg
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Old 22nd July 2004, 02:56 AM   #12
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Thanks for the suggestion. I think that inverting type challenge me to design balanced GC more than non inverting type. But I think that my new design might be better. neither non inverting and inverting type.
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Old 22nd July 2004, 06:00 AM   #13
djk is offline djk
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It helps to have input bias.

If using an FET opamp like an OPA604 use 470K from pin 3 to ground on both U2 and U3.
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Old 22nd July 2004, 07:55 AM   #14
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Is it not too high input impedance? What's your idea if R100k is connected pin 3?
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Old 22nd July 2004, 08:07 AM   #15
djk is offline djk
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Do you know how to read a spec sheet?

The input impedance of an OPA604 is 10^12 ohms

(1,000,000,000,000)

Virtually anything will work, your design had nothing.

Nothing doesn't work.
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Old 23rd July 2004, 03:03 AM   #16
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Yes, I know how to read spec. sheet but at that time I had no spec sheet on my hand, I just downloaded it to read the spec. Anyway, I have simulated with both input impedance 470k and 47k by PSpice. The output waveform results indicated me that 47k better than 470k. Eventhough the simulation results indicated 47k better but I will try the both because in actually maybe R470k will be better. By another thing, R470k is matched with C 0.1uF that is cheaper than C 1uF.
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