Hi guys, need advice with the output stage bias setting, as title says.
According to this document, page 11, 6.2 ,and onwards:
http://www.ti.com/lit/an/snaa045a/snaa045a.pdf
and with this other document:
http://www.eettaiwan.com/STATIC/PDF/200811/20081121_NS_AN01.pdf?SOURCES=DOWNLOAD
the recommended bias is 150mA per output device for best tradeoff between THD and dissipation.
Output devices are 3 pair of 2SK1530/2SJ201.
I don't want to screw up things so I want your thoughts about this; that way you will also help me check out my understanding as value seems rather high and heatsinks run warm as expected with this bias figure. Tables and graphics seem to confirm the bias value is correct but a lot of brains work better than just one
Find attached a somewhat gross circuit schematic.
This is how the whole thing looks so far. ready to finish it and open a specific thread about the build.
According to this document, page 11, 6.2 ,and onwards:
http://www.ti.com/lit/an/snaa045a/snaa045a.pdf
and with this other document:
http://www.eettaiwan.com/STATIC/PDF/200811/20081121_NS_AN01.pdf?SOURCES=DOWNLOAD
the recommended bias is 150mA per output device for best tradeoff between THD and dissipation.
Output devices are 3 pair of 2SK1530/2SJ201.
I don't want to screw up things so I want your thoughts about this; that way you will also help me check out my understanding as value seems rather high and heatsinks run warm as expected with this bias figure. Tables and graphics seem to confirm the bias value is correct but a lot of brains work better than just one
Find attached a somewhat gross circuit schematic.
This is how the whole thing looks so far. ready to finish it and open a specific thread about the build.
An externally hosted image should be here but it was not working when we last tested it.
BJT output stage needs either ClassA biasing, or optimal ClassAB biasing.
The same does NOT apply to FET output stages.
The more bias current the better the performance.
Borbely suggested a minimum of 500mA of output bias irrespective of how many pairs are adopted.
eg. 1pair use 500mA/pr, 2pair use >=250mA/pr, 3pair use >=167mA/pr
The same does NOT apply to FET output stages.
The more bias current the better the performance.
Borbely suggested a minimum of 500mA of output bias irrespective of how many pairs are adopted.
eg. 1pair use 500mA/pr, 2pair use >=250mA/pr, 3pair use >=167mA/pr
Cool Thanks Andrew, as always for your input. Glad you confirmed I'm heading in the right direction.
Good tip about splitting the required bias over the output pairs used. For lack of information in that respect I assumed the bias required was for each output pair, provided more than one pair is to be used.
Will report back as soon as the project is finished. So far works fine with zero hum. As you discern in the pic is a dual mono setup, with fully regulated power supplies.
Thanks Andrew, as always for your input. Glad you confirmed I'm heading in the right direction.Good tip about splitting the required bias over the output pairs used. For lack of information in that respect I assumed the bias required was for each output pair, provided more than one pair is to be used.
Will report back as soon as the project is finished. So far works fine with zero hum. As you discern in the pic is a dual mono setup, with fully regulated power supplies.
Last edited:
- Status
- This old topic is closed. If you want to reopen this topic, contact a moderator using the "Report Post" button.