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Old 8th January 2013, 07:40 PM   #171
KSTR is offline KSTR  Germany
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Argh, breadboarding setback today.
The multiple paralleled "capacitor strips" that I planned to use didn't work out as good as expected, loop area and hence inductance is still too high, 1.5mm PCB thickness together with non-optimum geometry (long and narrow strips) took its toll... so they're worse than a good compact PCB with them array'ed up in 2D instead of just lining them up in two rows....
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Old 8th January 2013, 07:47 PM   #172
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Did you use more than 7 caps parallel?
Although two caps may internally reverberate at the same time as one cap, manufacturing variances (in 10% or 20% tolerance capacitors) begin to foil paralleling ideas whereby the more you parallel, the more slightly different noises there are to add up to the worst capacitor ever made by the hand of man. I've seen the practical limit for no-ballast paralleling recur at about 7 caps parallel in many examples. I hope that helps.
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Old 8th January 2013, 08:01 PM   #173
KSTR is offline KSTR  Germany
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This is a geometrical issue, the build has to much intrinsic inductance so that the reduction by paralleling 30pcs. 47u/50V did NOT result in 30 times lower ESL the way I've set them up (but ESR did decrease as expected).

Of course there is something to your point of NOT to parallel too many identical caps to avoid concentrating any ill-effects like a mechanical resonance or any spooky ESR characterstics and such things that one might encounter for any specific make/model of cap...
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Old 9th January 2013, 06:58 AM   #174
gootee is offline gootee  United States
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Quote:
Originally Posted by KSTR View Post
This is a geometrical issue, the build has to much intrinsic inductance so that the reduction by paralleling 30pcs. 47u/50V did NOT result in 30 times lower ESL the way I've set them up (but ESR did decrease as expected).

Of course there is something to your point of NOT to parallel too many identical caps to avoid concentrating any ill-effects like a mechanical resonance or any spooky ESR characterstics and such things that one might encounter for any specific make/model of cap...
I don't know about concentrating any identical ill effects. But the more caps in parallel the more it should dilute any defect or ill effect that is not identical in all caps, and the less dependent the array will be on any one cap's properties.

In Terry Given's explanation (in this forum) of the array's geometry optimization, he specifically mentioned not making the arrays long and narrow, because the current needs to spread across the plane to be shared by all of the caps, as well as possible, in much the same (mathematical) way that heat spreads. His suggestion was to use a shape approximating a square, with the input at the middle of one side and the output at the middle of the opposite side. He did also mention offsetting the rows, but mainly for better cooling (by making any air go around all of the caps, instead of just rushing through corridors between rows of them).
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Old 9th January 2013, 08:43 AM   #175
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Yeah, Terry has it right!

I'll try 200m copper foil today with very thin insulation between them, in about 40mm x 40mm square shapes. These should fare much better at RF than the 20mmx80mm strips of 35m with 1.5mm spacing.
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Old 9th January 2013, 11:32 AM   #176
redjr is offline redjr  United States
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Hi Klaus, -

Not exactly sure what type of array you're trying to proto for the 7294, but I was wondering if something like this is what you're after? Maybe not as large of an array. I have not used this particular board, but have thought about getting one just to have around for a future project.
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Old 9th January 2013, 11:52 AM   #177
KSTR is offline KSTR  Germany
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That board sure is nice for the price but using an obsoleted capacitor type (Nippon Chemicon KMY), also it's not low impedance as does not use solid copper planes.

However, as a first filter/reservoir bank it might do well (with enough series resistance with the diode bridge).
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Old 9th January 2013, 05:24 PM   #178
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In using surface mount caps, one can make a vertical daughtercard with the caps on both sides. It reduces the board size dramatically. I still wouldn't put any caps at the "corners" of a square shape board. The 4 (or 8 if double sided) caps at corners would be the "most different" so I would omit them. I'm not sure how a vertically mounted double-sided approach affects your board layout, but assuming it has vias anyway, might as well mount caps to both sides of them. The surface mount computer caps are designed to tolerate "sideways" (any "mini-tower" computer), are available in tighter tolerances and generally have low ESR spec.

P.S.
I'm don't know how this applies to audio but it might work well for radio power supply. EDIT: The thought behind that was that radio worthy power supply can make a really high gain amp run nice and cool; however, you're doing low gain amp with added compensation, and it will probably ignore RF, which is a really much easier approach. When I was reading through all this, it seems that "Plan A" and "Plan B" got mashed together resulting in added complexity that is not required in all cases. Maybe it would be nice to separate the two approaches so that they can be compared.
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Old 9th January 2013, 06:38 PM   #179
KSTR is offline KSTR  Germany
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I'll try 200m copper foil today with very thin insulation between them, in about 40mm x 40mm square shapes. These should fare much better at RF than the 20mmx80mm strips of 35m with 1.5mm spacing.
It works, much better than the long PCB strip. Isolation is only about 200m thickness (two layers of paper backed adhesive tape), reducing loop area to the practical minimum. Analyser says than this 40 x 40mm copper foil square has a neglegible contributing inductance and resistance, that's what I need to tailor the supply with a solid baseline, without doing PCBs first....

Last edited by KSTR; 9th January 2013 at 06:44 PM.
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Old 9th January 2013, 06:43 PM   #180
KSTR is offline KSTR  Germany
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PCB will quite likely have a mixture of THT and SMT caps. I'll check out the option of vertical bypass/supply daughterboards, this might be a good idea to pack additional (but optional) capacitance into a given space.
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