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|17th April 2012, 07:40 PM||#1|
4 Channel LM4780
I currently have an Audisector LM4780 kit running and I love it.
I am now looking to run a Bi-Amped setup with PLLXO's for the Low/Mid section of a 3-Way.
The Mid/High will be handled with a standard LR2 Passive XO.
Question 1: My current LM4780 is setup in stereo mode w/ 300VA Toroid Trafo & 10,000uf/rail, would this be ok to add the second LM4780 to the supply with this P/S setup?
Question 2: Will this P/S configuration cause any "Dynamics" issues when using the first 20-30wpc @ 4 ch?
Question 3: How would I calculate the needed parts for a 150hz PLLXO?
|26th January 2013, 09:49 PM||#5|
Join Date: Nov 2006
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That's actually a fairly-complicated question, even for a single chipamp. It is better to have too much than too little, in terms of both Volt-Amps and Volts RMS (and also in terms of reservoir capacitance and decoupling capacitance).
You can try out different combinations of transformer parameters and capacitance (and resistance and inductance) and loads, et al, using my power supply simulation spreadsheet, downloadable from the post at Power Supply Resevoir Size (for the Excel 2007 version; the Excel 97-2003 version is at Power Supply Resevoir Size , but it doesn't have the "measurement from plots" functionality). The paper describing the spreadsheet and its development is downloadable from the post at Power Supply Resevoir Size .
You can also calculate the minimum reservoir and/or decoupling capacitance that would be needed in order to supply a single sinusoid's current to the load at any frequency, with the equations at Power Supply Resevoir Size .
(17a) C ≥ 2∙Δi / ( 2πf∙(Δv - (ESR∙Δi)))
gives the capacitance value, C, that would be required in order to supply the current for the first half-cycle of a sine signal of frequency f (in Hz), with 0-to-peak amplitude Δi Amperes, while causing the voltage across the capacitor to dip by no more than your choice of Δv Volts. (The other rail does the other half-cycle.)
To use equation (17a), it will probably be easier to first set ESR to zero, calculate a C value, find an estimate for the ESR for that C value at the frequency being used, and then re-calculate the C value with the ESR value.
NOTE that we need to try to make the ESR be much less than our desired Δv/Δi (i.e. the PSU impedance seen by the load). Otherwise, the required capacitance value will be excessive (because the denominator in (17a) gets close to zero).
An APPROXIMATE equation, that is similar to (17a), but uses Voltage Rating instead of ESR, and which is for electrolytic caps ONLY, is:
(18): C ≥ 2∙Δi ((0.04πf / VR) + 1) / (2πf∙Δv) [approximate, for electrolytic cap, only; VR=Voltage Rating]
And yes, the current for the load mostly ALL comes straight from the reservoir and decoupling caps! See the image at: Power Supply Resevoir Size !
While I'm at it, I will mention to not forget about the decoupling caps, which should be very close to the chip power pins. While the lower-frequency needs are covered by (17a) above, chipamps also require high-frequency transient currents, even beyond what can be used in the music itself, since the feedback loop will be trying to correct high-frequency harmonics, etc. We can calculate the needed minimum capacitance, to support the high frequencies. BUT, we must also then calculate the maximum tolerable inductance, which will usually then provide the maximum DISTANCE of the caps from the power pins.
Note, too, that while the lower frequencies can come from the power supply reservoir caps, the inductances of the power and ground rails will then cause more rail-voltage disturbances.
Anyway, the decoupling cap and maximum tolerable inductance calculations were derived starting at the post at paralleling film caps with electrolytic caps . Note that there might be some arithmetic errors, there, and also note that the estimate for the self-inductance per unit length of conductor (or cap lead-spacing) is usually taken as 1 nH per mm.
Last edited by gootee; 26th January 2013 at 10:11 PM.
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