Ive ordered a dual mono kit from chipamp.com. Everything is working except that when I meause the OUT (to speaker) and OUT GROUND (to speaker) It shows that OUT is - and OUT GROUND is +. Ive also meausured between OUT and CHASSIS GROUND and I get the same that OUT is - and CHASSIS GROUND is +.
The funny this is that it plays good whether I connect the speaker to OUT or OUT GROUND.
Here is a link to the assembly guide and scheme http://chipamp.com/docs/lm3886-manual.pdf
Hope anyone can assist me in this!
Thanks!
BR
GM
The funny this is that it plays good whether I connect the speaker to OUT or OUT GROUND.
Here is a link to the assembly guide and scheme http://chipamp.com/docs/lm3886-manual.pdf
Hope anyone can assist me in this!
Thanks!
BR
GM
if output plus is the minus and output minus is the plus...just invert them!. I guess you made a mistake in the wiring.
if output plus is the minus and output minus is the plus...just invert them!. I guess you made a mistake in the wiring.
Of course I alreaddy checked that and they are not mixed!
To be more clear.
The OUT GROUND is 0V and the OUT is -59mV so the out is actually a phase its just that its below zero. Why is this?
I called a friend with the same kit yesterday and he had the same issue. He wasnr aware of it and has been listening for a year very satisfied...
Strange
I talked with my friend who has the same kit. He has the exact same issue. He didnt know about it and he had been listening for almost a year very satisfied. Maybe this is correct..?
Anyways, since I have it in both channels and my friend has it in his both channels it cant be a soldering issue. Ive been soldeirng for 15 years so Im quite sure theres nothing wrong there. Im using a good weller station with appropriate temp and a suitable solder tip.
I know... The question is. Why are my dc offset negative?
Both my PSU's are giving the correct voltage out... and everything is properly connected.
Simply because the chip "decided" to do so. No worries, the specification for offset voltage is always to be understood without sign, magnitude only
Its down to transistor characteristics. Some have more gain.
It just so happens yours is negative.
The values you have given are nothing to worry about.
Setting myself up for a big fall here.
Mitigating statement :- im far from being an expert.
Here goes :- Current flows into the positive (+ve) i/p of LM3886 from the grounded 22K resistor (npn long tailed pair) so the votage at the +ve i/p is -ve (wrt ground) which drives the voltage on the o/p -ve.
The LM3886 dives the V on the -ve i/p to try and match the V on the +ve i/p with the result that the o/p goes to zero V ( no offset volts ).
However according to the spec it can take the -ve to be 10mV more -ve than the +ve for this to happen . Therefore something has to give and the result is a -ve offset voltage at the o/p .
Im making a lot of assumptions here .Mainly that the resistances ( with DC flowing through them ) are equal on the +ve and -ve i/p circuits and that there are not any capacitor leakage currents and the list goes on.
Am now cowering in the corner anticipating expert critique.
Mitigating statement :- im far from being an expert.
Here goes :- Current flows into the positive (+ve) i/p of LM3886 from the grounded 22K resistor (npn long tailed pair) so the votage at the +ve i/p is -ve (wrt ground) which drives the voltage on the o/p -ve.
The LM3886 dives the V on the -ve i/p to try and match the V on the +ve i/p with the result that the o/p goes to zero V ( no offset volts ).
However according to the spec it can take the -ve to be 10mV more -ve than the +ve for this to happen . Therefore something has to give and the result is a -ve offset voltage at the o/p .
Im making a lot of assumptions here .Mainly that the resistances ( with DC flowing through them ) are equal on the +ve and -ve i/p circuits and that there are not any capacitor leakage currents and the list goes on.
Am now cowering in the corner anticipating expert critique.
Nah, you got it about right.
The three main things that affect offset are:
A) The base-emitter voltages of the LTP transistors may be different, so the +in and -in pins may be at a slightly different voltage.
B) The LTP transistors may have different current gains, causing a difference between the currents flowing into the +in and -in pins.
C) There may be different resistances from the +in and -in pins to ground. In this case there's 22K resistors for both but it looks like there's no capacitor between the volume control pot and +in. In that case the actual resistance between +in and ground will depend on the volume control setting. I'd expect the DC offset to be worst with the volume turned all the way down.
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