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Old 28th November 2011, 09:28 PM   #21
gootee is offline gootee  United States
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Quote:
Originally Posted by quadtech View Post
Gootee, is this what you mean for the C1, C2 caps?
It's done in Eagle, and I can post the files here if the layout is ok.
The ones I was looking at are now labeled C5 and C6. They are the 0.1 uF bypass/decoupling capacitors for the chip's power pins. They are now better than before but should actually still be pushed a little closer (both could be moved to the right, on your latest layout).

Last edited by gootee; 28th November 2011 at 09:33 PM.
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Old 28th November 2011, 09:46 PM   #22
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Hi,
Why so long GND path between main caps? Rotating the lower cap 180 degrees and ground in the middle saves a lot of thack length. Power input would then be (from top): V- GND V+.
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Old 29th November 2011, 01:25 AM   #23
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Quote:
Originally Posted by gootee View Post
The ones I was looking at are now labeled C5 and C6. They are the 0.1 uF bypass/decoupling capacitors for the chip's power pins. They are now better than before but should actually still be pushed a little closer (both could be moved to the right, on your latest layout).
That's because I am a different person than the original poster
I was hoping to illustrate your point with a pic of a layout which I did.
For the OPs benefit, I am posting the eagle files, incorporating
the suggestions.

Notes:

1) SGND and PGND points are brought out separately.
2) If you need external mute, do not populate Rm1.
3) Verify and use at your own risk.
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File Type: png lm3886brd.png (64.1 KB, 325 views)
Attached Files
File Type: zip lm3886-eagle.zip (59.7 KB, 48 views)
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Old 29th November 2011, 03:14 AM   #24
gootee is offline gootee  United States
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1. Isn't there clearance UNDER the chip so that the V-'s 0.1 uF bypass cap could connect right next to the pin? Might have to thin the power trace a little in order to extend a small ground trace around the back of the chip pads. A 0.1 uF X7R ceramic capacitor would work best there, probably, and they are extremely small (like 0.2" LS (lead spacing), 0.2" L x 0.2" H x 0.125" W).

2. If the two 0.1 uF caps got pushed under the chip or between its pins, then the two 2200 uF caps could be moved closer. Just make sure that there is SOME clearance between them and the chip and heatsink, since heat is bad for electrolytics.

3. Connect the Zobel cap RIGHT AT the chip pin.

4. The 220p cap and the 880 (?) R (R3) need to go to the left as much as possible, closer to the pins. The 220p could also angle toward the rear pin. Then the 10K could also go left and be angled similarly, and the 1K and 22K could go left to connect closer to the input pin. Wait. Scratch that. ACTUALLY, it looks like the 10K should just go behind the back row of pins. Then maybe you could pull R1 and R2 way in and run the cmute trace around the outside (rear) of the 220p and under R1 and R2! And in that case, a 220p NPO ceramic should fit directly against the input pins, under the chip. Then the input resistors can come all the way in. Now we're getting somewhere! [Resistors for amplifier input pins (especially the negative input) should always be connected right AT the pin, if possible, so there's as little stray inductance as possible. Ditto for the bypass caps at the power pins.]

5. Need to fill in to remove all acute angles, such as around pads. Some appear to be "tangentiallly" connected. Fill the gaps. They are "etchant traps".

6. Remove the copper from the drill holes, if possible.

7. Should the rear face of the chip be right at the rear edge of the board, for easiest heatsink attachment?

8. Suggest extending traces (same width as pads) from input cap pads toward each other, in case someone needs to drill for different lead-spacing.

Last edited by gootee; 29th November 2011 at 03:38 AM.
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Old 29th November 2011, 03:53 AM   #25
gootee is offline gootee  United States
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The signal input ground reference point should be run separately (i.e. with a separate wire), all the way back to the star ground on the main power supply board (probably between the main smoothing cap ground connections?).

The signal input and signal input ground-return traces (and wiring) should stay absolutely as close together as possible, everywhere. I would go to the trouble of changing the ones near the input cap, so that they are right against each other, with a minimum gap between them, for absolutely as much of their length as possible, right up to the input-to-ground resistor. No need to let the capacitor width determine the distance between the traces. Maybe even put the cap OVER the ground-return trace. [The idea is to have zero "enclosed loop area", in order to not have any currents induced in the loop by time-varying magnetic or electromagnetic fields in the air, which can be a major and common source of power supply hum (not to mention RFI). See "Faraday's Law".]

You might also want to leave space for a resistor and parallel inductor in series with the output.

Last edited by gootee; 29th November 2011 at 04:21 AM.
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Old 29th November 2011, 04:38 AM   #26
gootee is offline gootee  United States
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You MIGHT want to also have a separate isolated ground return for the output Zobel network.

I'm not sure about the Mute circuit's ground return but I suspect that it would be much better to connect it with the isolated input ground reference for its connection back to the power supply than to lump it in with the output ground. Either do that or run it completely separately.

Last edited by gootee; 29th November 2011 at 04:42 AM.
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Old 29th November 2011, 09:43 AM   #27
AndrewT is offline AndrewT  Scotland
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Originally Posted by AndrewT View Post
......... Look at PIN2. It is not connected. You can use this spare PCB area to thicken traces.....................
............................you may find that very small ceramic caps make for excellent power pin decoupling. These can be fitted much closer to the Power PINs than those big 0.2" pin pitch film caps shown.
Quote:
Originally Posted by gootee View Post
C1 and C2 are too far from the chip's pins. ..................
Quote:
Originally Posted by gootee View Post
........... They are the 0.1 uF bypass/decoupling capacitors for the chip's power pins. They are now better than before but should actually still be pushed a little closer (both could be moved to the right, on your latest layout).
Quote:
Originally Posted by gootee View Post
1. Isn't there clearance UNDER the chip so that the V-'s 0.1 uF bypass cap could connect right next to the pin? Might have to thin the power trace a little in order to extend a small ground trace around the back of the chip pads. A 0.1 uF X7R ceramic capacitor would work best there, probably, and they are extremely small (like 0.2" LS (lead spacing), 0.2" L x 0.2" H x 0.125" W).

2. If the two 0.1 uF caps got pushed under the chip or between its pins, then the two 2200 uF caps could be moved closer. Just make sure that there is SOME clearance between them and the chip and heatsink, since heat is bad for electrolytics.
you are being told repeatedly that HF decoupling must be moved closer !!!!
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Old 29th November 2011, 09:54 AM   #28
AKN is offline AKN  Sweden
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Hi,

I think decoupling is close enough. Also, small caps in parallel with low ESR caps can cause resonance with corresponding high impedance peaks at high frequency. It's recommended to use standard electrolytic if paralleled with small low loss caps.
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Old 30th November 2011, 05:39 AM   #29
gootee is offline gootee  United States
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Quote:
Originally Posted by AKN View Post
Hi,

I think decoupling is close enough. Also, small caps in parallel with low ESR caps can cause resonance with corresponding high impedance peaks at high frequency. It's recommended to use standard electrolytic if paralleled with small low loss caps.
I am sorry but I must disagree with your "close enough" guess. On what do you base it? The inductance which is proportional to the length of the PCB trace between the pin and the bypass capacitor is a problem that needs to be mitigated. What length would you say would NOT be close enough and why? Anyway, accepted best practice is to make the distance as close to zero as possible and always less than 2 mm (and less for high-frequency circuits). So if that's easily-enough done then why not (especially when we're talking about a PCB design, which might be around for a long time and might be used by many)?

Yes, you make a good point, that a small cap can form a resonance when paralleled with a larger cap. But that's due to the _inductance_ of the larger cap and the small capacitance (combined with the inductance presented by the PCB traces, et al) forming an LC resonance, which can be a problem if there is too little damping (capacitor ESR). But lower ESR makes a better bypass or decoupling cap. And the 2200 uF caps could use low ESR, maybe especially at low frquencies where a "low ESR" rating is meaningful. That's one of the reasons why I suggested using an X7R ceramic for the 0.1 uF, and not a film cap or an NPO ceramic.

ESR of electrolytic caps varies significantly with frequency. At high frequencies (where the resonance would be), basically _every_ large electrolytic capacitor (not just "low ESR" types) will have a very low ESR. So a small cap that is paralleled with a relatively-large electrolytic should basically never be a "low loss" type, such as film or NPO/C0G ceramic, unless one is a very careful and sophisticated designer, or, knows how to design an optimal snubber resistance and add the proper series capacitance value to it to prevent excessive dissipation.
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Old 30th November 2011, 11:15 AM   #30
AKN is offline AKN  Sweden
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Quote:
Originally Posted by gootee View Post
I am sorry but I must disagree with your "close enough" guess. On what do you base it?
Hi gootee,
Do we discuss the same layout? Decoupling is in fact very close.

Well, first of all, the data sheet for 3886 does not mention any requirement that decoupling must be placed right at the pins. However, the datasheet does recommend that decoupling should be placed as close as possible next to the chip. I do think that proper decoupling is well addressed in the latest layout shown at this page. Where do we draw the line?
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