Input resistors query.

[Omega_Void]

In the application schematic there's the 22k input resistor, in parallel with a 1Meg resistor preventing the input cap developing charge.

It occurred to me that a similar input impedance would be achieved by using two 43k resistors instead.

Would this be a bad idea, a good idea, or make no difference? I'm too stupid/ignorant to work it out.

Thanks.

[analog_sa]

Originally Posted by Omega_Void

It occurred to me that a similar input impedance would be achieved by using two 43k resistors instead.

The 22k resistor has its value chosen so that both inputs of the opamp will be fed by similar dc resistances thus similar bias currents. This will minimise offset.

[Omega_Void]

Originally Posted by analog_sa

The 22k resistor has its value chosen so that both inputs of the opamp will be fed by similar dc resistances thus similar bias currents. This will minimise offset.

D'oh! Of course. I had that info somewhere in my head, but it's so hard to keep track of everything.

Thank you.

[Omega_Void]

But... in the datasheet the feedback resistor is only 20k. Surely then the -in pin sees about 2k less DCR than the +in?

Sorry if I'm overlooking something obvious, but don't get the values shown.

[AndrewT]

Originally Posted by Omega_Void

but don't get the values shown.

what values shown?

[Omega_Void]

Originally Posted by AndrewT

what values shown?

It's the LM1875 datasheet I'm looking at.

I don't understand the resistor values shown on the datasheet schematic in that the DC resistance seen by the +in looks to be 2k greater than the DC resistance seen by the -in.

Why 22k on the input and only 20k in the feedback? It seems to invite a DC offset without conferring any obvious advantage.

[AndrewT]

Hi,
yes, National show a slight mismatch in the resistances presented to the two inputs.
The mismatch is only 2k.
Multiply this by the worst case input offset/bias current and you get the added output offset that the chip will generate.

If the NFB cap were omitted the mismatch changes from 2k to 21k05. That would increase the output offset 200times from <=4mV to <=800mV

I would change both to 27k for 28times gain. Some builders seem to think that these chips sound slightly better when the gain is that bit higher. Increased gain increases the phase and gain margins, resulting in a more stable amplifier that is less sensitive to reactive loading.

[Omega_Void]

Thank you very much! That's a handy tip.

[abraxalito]

Originally Posted by AndrewT

Hi,
yes, National show a slight mismatch in the resistances presented to the two inputs.
The mismatch is only 2k.
Multiply this by the worst case input offset/bias current and you get the added output offset that the chip will generate.

In the typical case (for 0.2uA) this is 4mV, worst case its 40mV. Since the input offset voltage is typically 1mV, the ideal difference between the two impedances would be below 500R. I agree with Omega, its rather pointless to have these values different.

If the NFB cap were omitted the mismatch changes from 2k to 21k05. That would increase the output offset 200times from <=4mV to <=800mV

Yes, definitely not at all recommended. It gets worse than that in the worst case.

I would change both to 27k for 28times gain. Some builders seem to think that these chips sound slightly better when the gain is that bit higher. Increased gain increases the phase and gain margins, resulting in a more stable amplifier that is less sensitive to reactive loading.

The downside of this is slightly increased distortion (and slightly more noise) as less NFB available to correct the open-loop non-linearities. So take your pick - it depends on your load. Chip amps can also be run at lower gains with appropriate compensation. Lower gains mean you can get away with no electrolytic and still keep the output offset manageable