Pa100

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What load are you going to connect that makes you choose a parallel setup with only 17 V rails?

Consider to move C5 and C6 to the other side of IC2 to have them nearer to the power supply pins. Also use another pair of them on IC1's supply pins.
For my taste the speaker traces are to near to the input traces where they run parallel. Could work, but could as well cause issues.
Do the fixing screws all fit? It looks as if a screw head would not pass by C4 and as if the other three would at least be in intimate contect with IC1, J1, J8 and J9.
 
What load are you going to connect that makes you choose a parallel setup with only 17 V rails?

Consider to move C5 and C6 to the other side of IC2 to have them nearer to the power supply pins. Also use another pair of them on IC1's supply pins.
For my taste the speaker traces are to near to the input traces where they run parallel. Could work, but could as well cause issues.
Do the fixing screws all fit? It looks as if a screw head would not pass by C4 and as if the other three would at least be in intimate contect with IC1, J1, J8 and J9.

The schematic says +/- 37 VDC, however it should be +/- 34 VDC since I am planning on using a 2 x 25 VAC transformer. Using speakers that drops down to 4 Ohm.

Concerning C5 and C6, I agree that they are too far away from the supply pins and I have been wanting to move them closer and add another pair to the other IC, but just havent gotten around to do it yet.

As for the speaker traces and their close proximity to the input traces I had thought about it as well, but came to the conclusion that it should not be a problem. However, since I am making the boards myself, it can easily be changed if it indeed does turn out to be a problem.

The fixing screw pads are 8 mm and since I am going to use M3 fixing screws, it will not a be a problem, should be a clearance of about 1 mm from the edge of the screw pads to the screw head.
 
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Neutrality,
yes, Pacific missread your schematic, mostly because you have used an enormous pixel width but with tiny notation.
Look at your posted pics and see how much you can read clearly. Did you even check after posting?
Look at the PCB layouts. What has happened to the width:height ratio?
Are the various colours used suitable to view the PCB traces?
 
The schematic isnt good, I agree.

However the PCB layouts are just fine, theres nothing wrong with the width:height ratio.

As for the colours, why wouldnt they be suited? Where I work, the top layer is almost always red and the bottom almost always blue. Thats how our PCB layout program is setup as default and I never heard anyone complain about it before.

Anyway, the design is outdated, working on a PA100 in the inverted configuration, with an opamp as a buffer in an inverted configuration as well, giving me noninverted input>noninverted output. Using a 50K pot to adjust DC offset.
 
Maybe I'm colour blind, but that spread of vermilion with narrow yellow? lines interspersed with blues and black and brown is very hard on my eyes.
Possibly the same colour range as most others post, but one of the worst for legibility I can remember.
Why are the pads appearing as ovals/ellipses? width:ratio?
 
Why are the pads appearing as ovals/ellipses? width:ratio?

But yet the corner mounting holes are round?

There are 5 fast on connectors, their pads are slightly oval and thats how they are supposed to be. The same goes for the PCB mounted RCA/Phono connector.

No rule saying that everything has to be round or square.

Theres nothing to see here folks.....
 
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Theres nothing to see here folks.....


Hi Mr. N
Are you mad now that people have some suggestions toward helping you improve your design or it's presentation? If so please disregard my comments below.
Have you considered using 2 ground planes ie separation of low level signal returns from power?
Agree with Pacific on adding more power decoupling caps closer to the further of the chips> Perhaps 220uF in addition to 100nF because ESR is more defined at the potential near the frequency of oscillation. I think stable power distribution or tighter coupling of these chips is key to paralleling them.
What is your plan on reducing/tolerating initial DC offset?
 
Hi Mr. N
Are you mad now that people have some suggestions toward helping you improve your design or it's presentation? If so please disregard my comments below.
Have you considered using 2 ground planes ie separation of low level signal returns from power?
Agree with Pacific on adding more power decoupling caps closer to the further of the chips> Perhaps 220uF in addition to 100nF because ESR is more defined at the potential near the frequency of oscillation. I think stable power distribution or tighter coupling of these chips is key to paralleling them.
What is your plan on reducing/tolerating initial DC offset?

Im not mad, my last comment was because people talked about the oval pads as if something was wrong and there isnt, some of the pads are supposed to be oval and so the width ratio is just fine. :)

I have already started implementing changes to power decoupling as well as the changes to my overall design I mentioned in another post.
 
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