LM1875, TDA2050 on 2 Ohms

[johnr66]

If I use one of these chips at reduced Vs, I wonder if I can use 2 Ohm loads? I guess the crux of the question is, if it just the peak current that limits minimum load impedance?

I want to use the chip with a 19 volt (laptop brick) single supply with the IC wired up in single supply mode. I understand Po is reduced, but I can compensate a little by using two 4 ohm speakers in parallel. Sure there are other ICs, but I have many of these in the parts drawer.

Should I compensate the input bias current by using a lower resistance resistor since Vs is about 1/2?

[infinia]

Originally Posted by johnr66

I understand Po is reduced, but I can compensate a little by using two 4 ohm speakers in parallel. Sure there are other ICs, but I have many of these in the parts drawer.

I think it would be much better to run more of those chips to each speaker rather than paralleling the drivers. or better yet look into chips like TI's class D if spl vs battery time is important. Start looking at Pout vs Pdiss curves for different loading.

[ratza]

Originally Posted by johnr66

Should I compensate the input bias current by using a lower resistance resistor since Vs is about 1/2?

Input bias current has nothing to do with the load. It only affects the input impedance: higher bias current = lower resistor values.

[kuldeepsingh]

give a try, but the chips will run very hot.

[johnr66]

Originally Posted by ratza

Input bias current has nothing to do with the load. It only affects the input impedance: higher bias current = lower resistor values.

No kidding. I was referring to Vs being lower meaning less current on the input bias, so using a smaller value resistor to make up for it unless the the ICs preamp circuit is using a constant voltage or current internally. I guess I'll just put a meter across that resistor and measure it while adjusting the supply voltage. Didn't think of trying that before.

[johnr66]

Originally Posted by kuldeepsingh

give a try, but the chips will run very hot.

Power dissipated is a function of the rms voltage across the output transistors multiplied by the current. Running the chip at around 1/2 the supply voltage will greatly reduce dissipation while increasing load current will increase it. Since these counter one another, the chip should be fine.

I'm just wondering if doing this will throw something out of balance that I'm not thinking of. I'm beginning to think it will do no harm as long as the current is kept within the design of the IC.

[DigitalJunkie]

Parallel a couple chips?
I did that with some LM4950's to run a 4ohm load (they're only rated for 8ohms in BTL mode) and it worked out well. Just don't forget the low-value current sharing resistors on the outputs.