LM1875 nested Gainclone

[linuxguru]

I don't necessarily understand the Technics schematic of the previous posting - it seems to be entirely small-signal, i.e. pre-amp only. I'll look into it later to try to glean insights, but for now I'll skip it.

In the patent diagram in post #9, the closed-loop voltage gain of C can be calculated. There's voltage-series feedback through R3 and R4, R5 and RL (not shown). Assuming ideal op-amps A and C (zero input offset, zero input current, infinite open-loop gain), and a lot of high-school algebra, we get the following expressions for the voltages at nodes J2 and J3:

Vj2 = Vo (1 + (R2 (R3 + R4 +R5) / (RL(R2 + R4 +R5)))) ..... (1)
Vj3 = Vo (1 + (R2 (R4 + R5) / (RL (R2 + R4 + R5)))) ..... (2)

Voltage gain of C is simply Vj2 / Vj3, which simplifies (after more algebra) to:

Vj2 / Vj3 = 1 + R2.R3 / (R2(R4 + R5) + RL(R2 + R4 + R5))

Since all the Rs are positive, we see that the voltage gain of C is necessarily greater than unity. That's a big relief, because that was also intuitively obvious just by inspecting the circuit topology in post #9, and it's nice to see that intuition doesn't conflict with the analysis.

In this particular case, the gain was greater than unity, but there may be other bridge topologies (notably the quad current-dumping topology), where the voltage-gain of the output stage is required to be 1 or very close to 1. This requires the use of unity-gain stable amplifiers, or alternatively, to attenuate the voltage input to the output stage by a factor equal to its minimum stable closed-loop gain, and set its closed-loop gain to the reciprocal of the attenuation factor to recover unity gain.

In the schematic of post #1, the attenuation is 1k/(1k+10k) = 1/11, and voltage gain of the LM1875 has been set to (1 + 10k/1k) = 11. The LM1875 is spec'ed to be stable at gains over 10, so it's stable as shown. For other chipamps with differently specified minimum stable closed-loop gains, we have to adjust these dividers accordingly. For the TDA7294, the minimum stable closed-loop gain is specified to be 24 dB => a gain of ~16 or higher.

[lumanauw]

Hi, Linuxguru,

in the formula

Vj2 / Vj3 = 1 + R2.R3 / (R2(R4 + R5) + RL(R2 + R4 + R5))

is it RL or R1? RL(not shown), is it load resistance?

Meanwhile, this is how the patent applied for power amps.

[lumanauw]

I found this on my computer

[lumanauw]

and this

[linuxguru]

It's RL, load resistance (not shown in the patent diagram). The SE-A100 schematic differs from the patent diagram in some respects - notably, the attenuator to the output stage is grounded in the SE-A100 (as it is in my nested gainclone schematic), but in the patent diagram of post #9, the load forms part of the attenuation network (this has consequences for stability under no-load conditions, etc.)

The schematic in post #13 is also a Technics-like topology, and has some conceptual similarity to my nested gainclone. The main difference is the impedance of the networks, as well as the low-impedance path from the chipamp to the load.

The schematic in post #14 is also a similar Technics-like topology. The main difficulty in realizing these in practice is the consequence of bridge imbalance. Not only could the small-signal front-end opamp go into current limit, its output stage could also be damaged. There's a need to isolate the output of the chipamp from the output of the op-amp, with a resistance of ~ hundred ohms, rather than a fraction of an ohm.

[lumanauw]

Hi, Linuxguru,

I try to calculate gain for amp C with this formula

Vj2 / Vj3 = 1 + R2.R3 / (R2(R4 + R5) + RL(R2 + R4 + R5))

R2=10ohm, R3=10k, (R4+R5)=1k, RL=600ohm.

With RL=600ohm, the gain is very near 1 (unity gain). I guess this means that amp C should be unity gain stable.

Why is in equation above there is no R1 at all?

[linuxguru]

> Why is in equation above there is no R1 at all?

Good question, and for a moment I feared that my math was wrong. Then I figured out why the math is right, and R1 doesn't enter the equations: The voltages at all nodes are fully specified by the rest of the circuit, and R1 will not enter the equations to calculate the node voltages.

With ideal op-amps (with infinite current sinking/sourcing capability), both sides of R1 are driven by norators (hypothetical devices that can source any current at any voltage). Hence, any value of R1 is admissible, and the voltages at each end of R1 will still remain the same - only I1 depends on R1.

[linuxguru]

After playing around in LTSpice for while, I came up with another nested gainclone concept similar to Walt Jung's composite op-amp/buffer. I dropped the feedforward path and retained some gain in the power op-amp stage, thus keeping the voltage swing at the output of the small-signal op-amp low. This allows the use of a jelly-bean ne5532 as the small-signal op-amp and still retain good performance.

Of course, one could substitute the ne5532 with something better, like an LT1208 or an LT1469 or an LM4562. However, it will been seen from the simulation results that the NE5532 does very well indeed when its swing is kept low - around 1 V peak. How well? The nested gainclone topology reaches ~ -120 dB THD20, mostly H2. In fact, almost all the distortion is even harmonic.

Here's the LTSpice simulation schematic - it uses a loop probe injection method, due to Tian et al (and simplified by Wiedman), to determine the AC small-signal loop gain, phase margin and stability. The sources Vi and Ii in the schematic are used to implement the probe - These do not enter the LTSpice large-signal transient analysis.

[linuxguru]

Here's the simulated THD20 FFT at 20W into 8 ohms. H2 dominates at ~ -120 dB, and the odd harmonics drop off very quickly below -150 dB.

[linuxguru]

Here's the simulated Loop Gain as function of frequency, using the Tian method. The phase margin at unity gain is comfortable at ~70 degrees. As a sanity check, it's also stable in large-signal transient analysis simulation.