is there a canonical LM3875 diyaudio.com circuit?

[travis]

I have some LM3875s and some transformers. What's the first point to point design that you've seen here that pops into your brain? The simpler the better.
I did search. The results when you search for thread titles that contain "lm3875" are legion.

[CJ900RR]

The example circuit from national.com



Simple, works well. Add decoupling-caps (0,1uF) as close to V+ and V- and of you go. Cs should be 1000-2200uF/35V.

[AndrewT]

Hi,
you could omit Ci from post2 to make a DC coupled amplifier.

But you must ensure that the pre-amp NEVER sends more than a few mV (<20mVdc) of DC to the power amplifier.

[peranders]

Andrew, your advice works most of the time but some LM3875 may have up to 10 mV offset times 20 or 30 (the gain) = 200-300 mV which is not dangerous to the speaker but possibly not desired.

[Peter Daniel]

Originally posted by peranders
Andrew, your advice works most of the time but some LM3875 may have up to 10 mV offset times 20 or 30 (the gain) = 200-300 mV which is not dangerous to the speaker but possibly not desired.

I measured at least 500 LM3875 chips and with a schematic above, 10k input impedance and no Ci, the offset was never more than 100mV (50mV being average).

[AndrewT]

Originally posted by Peter Daniel


I measured at least 500 LM3875 chips and with a schematic above, 10k input impedance and no Ci, the offset was never more than 100mV (50mV being average).

But he has 3k5 as max source impedance so he may get worse than your 50 to 100mV.

However, if Travis were prepared to drop both the NFB resistor values he could trim the DC output offset lower.

[seventenths]

I am very pleased with my results after following this:

http://myweb.tiscali.co.uk/nuukspot/...gainclone.html ,

but, it is easy enough to bread-board and test several circuits in the course of an evening if you are so inclined.


Have fun
7/10

[Peter Daniel]

Originally posted by AndrewT
But he has 3k5 as max source impedance so he may get worse than your 50 to 100mV.

To be precised, I was talking about the offset of the chip alone. When doing my tests, the source was not connected, intput shunted by 15K resistor.

Lowering the combined input resistance will always lower the offset, the source should not produce any DC offset, 20mV is way too much.

[AndrewT]

Originally posted by Peter Daniel


To be precised, I was talking about the offset of the chip alone. When doing my tests, the source was not connected, intput shunted by 15K resistor.

Lowering the combined input resistance will always lower the offset, the source should not produce any DC offset, 20mV is way too much.

Maybe in attempting brevity I did not explain myself sufficiently.
The NFB has 20K on it. If the DC blocking cap is removed then this drops to <1k.
Now 10k source resistance on the other input will make the output offset worse not better.
Reducing Rs below 3k5 will reduce the offset. Changing the volume from -6db will have this effect. But the circuit shown cannot drop the Rs below 1k.

[Peter Daniel]

I still don't see your point, my worst case measurements were with Rs 15k . Lowering Rs to 3k5 will only show lower offset, not higher. That was without DC blocking cap.

When Rs is getting close to zero, the offset will not neccessarily go to zero; after crossing zero, it increases in opposite polarity, usually lower voltage.