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Old 10th August 2007, 12:32 AM   #81
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Quote:
Originally posted by Russ White


No it is not current limited. At least according to the design engineer I called to ask.

How about a current-limited voltage regulator for the chip?
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Old 10th August 2007, 12:43 AM   #82
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Quote:
Originally posted by panson_hk



How about a current-limited voltage regulator for the chip?

That is a very interesting idea....
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Old 10th August 2007, 02:04 AM   #83
glennb is online now glennb  Australia
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Quote:
Originally posted by Russ White
I suppose the only way to know for certain would be to short the output with an ammeter.
Or to be slightly nicer, hook up the Fig. 3 test circuit in the datasheet with +/-50V rails and load the output with a 470 Ohm 5W resistor. Drive the amp with say a 1Khz sine wave and gradually turn up the wick until the output starts to clip on a CRO. The maximum output current capability is then simply Vpeak/R. Hopefully the chip won't expire.

The slew rate limit can also be measured by increasing the frequency until the output is a triangle wave, then measure the slope in V per microsecond. Ccomp influences the slew rate.

I just haven't had time to try this with my samples....
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Old 10th August 2007, 07:54 AM   #84
AndrewT is offline AndrewT  Scotland
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Quote:
Originally posted by panson_hk
How about a current-limited voltage regulator for the chip?
yes a CCS set to quiescent +20% and then shunt regulate that extra 20% to ground.
The chip is then protected at quiescent current level until the shunt starts to reduce it's demand to try to keep the supply voltage up, plus peak/transient demand from any supply caps after the CCS.
Simple and short circuit proof.
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Old 11th August 2007, 06:58 AM   #85
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I built the data sheet test circuit (Fig. 3) on a prototyping board as shown in the image. The circuit is powered by an unregulated +/- 22 VDC. The scope shows the output of a 1 kHz sinewave.
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File Type: jpg prototype.jpg (80.7 KB, 2769 views)
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Old 11th August 2007, 07:10 AM   #86
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The Cc in the prototype is 22 pF. I then measured some curves using AP S1. The output residual noise is about 45 uVrms (BW = 22 kHz). Several THD vs output level curves are shown in the pdf file (note the input impedance of S1 is 100 kHz). My next step is to load the circuit similar to that of headphone amp.
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File Type: pdf lme49810 test circuit prototype.pdf (9.8 KB, 719 views)
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Old 11th August 2007, 08:11 AM   #87
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Quiescent current Icc = 12 mA and Iee = 8 mA were measured. Does anyone have these data? Are they supposed to be not identical? Data sheet says Icc=11 vs Iee=13 mA. Output DC is 0.4 mV with input grounded.
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Old 11th August 2007, 09:03 AM   #88
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Hi,
what connections have you got to ground (0V)?
The output should be open circuit for checking output offset.
Will this chip operate correctly with both outputs unconnected?
If you know the ground currents then you can calculate the difference between Icc & Iee.
If there is zero ground current, then Icc=Iee.
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Old 11th August 2007, 09:22 AM   #89
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Quote:
Originally posted by AndrewT
Hi,
what connections have you got to ground (0V)?
The output should be open circuit for checking output offset.
Will this chip operate correctly with both outputs unconnected?
If you know the ground currents then you can calculate the difference between Icc & Iee.
If there is zero ground current, then Icc=Iee.

Input (IN+) is grounded via Rin. Am I answer your question?
Yes, offset was measured with output open circuit. The ground current is 4 mA, exactly the difference between Icc and Iee. Is it normal?
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Old 11th August 2007, 09:33 AM   #90
AndrewT is offline AndrewT  Scotland
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Hi,
you are getting 4mA flowing into the ground connection from Vcc.
Why do National show 2mA flowing out of the ground to Vee?
Your input pin ground current <1uA and is swamped by others.

Why is your circuit flowing in the opposite direction?

Is your 4mA the mute current?
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