sg3525an: need help desining test circuit
so..... i got a wild hair last night/evening to apply a switching design that i have had for a couple years, and now, i need to build a test board. i've been up all night researching, and repeatedly studying both the tl494 and sg3525. what i need to be able to do is adjust frequency and duty cycle, but here is the tricky part:
i would like to interrupt every 3rd, and also be able to interrupt every 3rd and 4th wave.
it looks like i can do this one of a few ways,
first, i could use a few transistors. One triggered to by the second output to simultaneously connect the sync to a second sg3525an, and trigger the error amp, which prevents fip-flop and output, for the one pulse. a second, triggered on by the pulse from the other 3525 output feeds into a third, which will only trigger at the end of the output pulse, cutting supply to the initial transistor to allow the cycle to begin again.
Second, it may be easier to use the single 3525an with only 1 output and build a 3-way and 4-way flip-flop, which i might need help with.
Third- i could use a flip-flop on a second cap for the oscillator to double the time and tie into another 3525, similar to option1.
...and, whatever other ideas.
a few questions i have:
the components i want to run from these would only be 200ma nominal, but may go over. what drivers would you suggest to run?
what transistors/fets would you suggest for the switching needs?
are there better options to fit my needs?
are there some good free circuit design programs, especially one that can make board images for washing?
any special characteristics of the 3525 i should be aware of?
i can get a list of the parts i have on hand but it is mostly the 3525an's, many common fets and outputs, like 3205's, 540/9540, 44n and some i would have to go back and check.
thanks for help,
What about a divide-by-n counter IC?
I no longer make boards. It's too easy to get PCBFabexpress to make them. Use a circuit board layout editor and send them the files. In about 2 weeks, you'll have a good quality professional board. For initial prototyping, use a breadboard.
There are a lot of circuit simulators but for this type of circuit, they aren't likely to be that useful. It's all switching and the speeds are relatively low so you can see all you need to see with a scope.
i'm having trouble finding a suitable counter that will alternate in cycles. they all seem to have only outputs that divide the signal into progressively lower frequency. i need all 3, or 4 outputs to be equal, original frequency, just alternating. i remember building a few different similar circuits in the 90's, off the 555 chip. maybe i should look in storage for my old notes.
i would also like to be able to go as high as 200khz, maybe higher, like 300-400hz. the 3525 should fit the bill there, but i would think there might be something better, or simpler...
I have no input here, but I am curious why you want to do the alternating skip?
i am wanting to study effects of arrays in different circumstances/application. more than 2, and more mailable than simple follower.
perhaps, i'll try to build a simple flip-flip-flip-flip-flop. hahaha. not sure if i can find something to meet the needs. still haven't found my old books for the switching arrays. i'm sure it'll hit me how simple, once i see it again, lol.
This may be easier with a PIC.
so, after doing a bunch of looking around, i finally came across a 74hc4017 decade counter/divider. looks like it can do exactly what i want off the 3525 signal. i should be able to use it with the 1, or 2 outputs, in case i want to double the frequency, to be able to run beyond max single out frequency. i still need to pick out some decent fet drivers that can take up to 7v, or so. hopefully without signal degradation, , but that would not be too big of an issue, since i can just run the final output through a 4066 and keep the rise/fall time to 6ms max, iirc.
few more questions:
-about the 4017, as the p-sheet is not too specific, or i have not read proper enough..
will it carry the proper duty cycle as it is fed into the clock, through the outputs, or simply stay on full? if not, i may need to find another ic, or go another route, like using a pwm on each of the outputs....
will i run into a problem with delay feeding the next in line unused output to trigger the master reset?
it mentions that all unused outputs must be held at vcc, or ground. it does not say if that is all that is needed to make it skip the unused outputs and switch seamless from the last used output, back to output 0.
as for input, and output current, it just says "+/-50ma" not too sure what that means. max deviation, or the max transferred?
what would be a good driver to use?
The TC442x series of drivers are generally good choices for most low frequency work. You have to remember, as you increase the frequency, the FETs will become increasingly harder to drive. If you're going to be using parallel FETs, this may be a design issue.
the gate capacitance is the direct cause of high frequency losses when driving MOSFETs. When i prototyped and built a digital atmel based regulated power supply, i used logic-level MOSFETs with the absolute lowest gate capacitance/on resistance i could find. Not cheap, nor easy. but do-able, I also put gate-clamps on the FETs to protect the CPU if they shorted for any reason.
okay, i ordered some of those, since i was placing an order for a few other things. i have a few questions on the 14018:
in the instructions to devide by 3, it states a "gate package needed to provide AND function. counter skips all 1's state" what does that mean? i take it "AND" stands for something, but not sure.
on the switching times, it appears each output goes low for 5 clock cycles, when set to devide by 10. how will it function when set to devide by 3? is this a preset switch dead-time, or can i control the length?
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