As long as the gate is being driven to below ~3v before the other FETs switch on, the drive circuit is OK.
The glitch in the gate signal is caused by the FETs switching on/off. The gates are capacitively coupled to the drains and when the drain transitions from high to low (or from low to high), it leaks into the gate of the FET. This is normal.
The glitch in the gate signal is caused by the FETs switching on/off. The gates are capacitively coupled to the drains and when the drain transitions from high to low (or from low to high), it leaks into the gate of the FET. This is normal.