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When is a clock not a clock?

Posted 29th September 2016 at 04:31 PM by Tam Lin

When it goes through a logic gate.

I heard that riddle in 1978 when I worked as a programmer for a computer startup in Silicon Valley. For some reason, it stuck with me although I didn’t appreciate its profundity until I started studying DAC design.
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Multi-Channel, High Sample Rate PCM

Posted 18th July 2016 at 01:36 PM by Tam Lin

Here is a multichannel implementation that continues the theme of high sample rate PCM with no logic chips in between the oscillator and the DACs. There are two variations: seven and fifteen channels using USB2 bulk mode transfers up to 1.536M samples per second. More channels and higher rates require USB3.

What I find appealing about this design is that it is easily bread boarded. For USB, use a Cypress FX2 evaluation board. It has a built-in quantum FIFO and packet buffering. For the oscillator, use a Si570 evaluation board. With it, you can easily switch between the 7 and 15 channel versions, 44.1K and 48K based sample rates, 16x and 32x oversampling, and 24- and 32-bit sample frames. For the DACs, use Twisted Pear CODs with SCK = BCK and the format switches set for DF bypass.
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High Sample Rate PCM – II

Posted 12th July 2016 at 01:24 PM by Tam Lin
Updated 17th July 2016 at 07:03 PM by Tam Lin (typo)

Theory tells us that each time the number of DAC chips is doubled the SNR increases by 3 dB. With 32 chips per channel, we should see a 15 dB increase. That is very good, but we can do better because there is no reason the paralleled DAC chips have to receive identical input data.

In essence, we have a 29-bit DAC for sample rates at or below 768K. For each 24-bit input sample value, we can provide a 29-bit value that produces an output current that is closest to the ideal. Accessing a 16MB look-up table 768K times per second is trivial for a modern 64-bit microprocessor. The table data comes from a one-time calibration procedure that analyses the DAC’s measured output performance for each possible input.

Above 768K, we are dealing with a delta that is obtained by scaling the difference between consecutive samples. Below 11.2896M, two or more chips are paralleled and a table lookup is used to improve accuracy.
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High Sample Rate PCM

Posted 2nd May 2016 at 12:13 AM by Tam Lin
Updated 12th July 2016 at 01:38 PM by Tam Lin (corrected typo)

With delta-sigma DACs pushing insane clock rates I wondered if a traditional multi-bit DAC could not do better. The fastest multi-bit I know of is the PCM1704, which has a max BCLK rate of 25 MHz. A 32-bit sample frame can run at 768 K samples per second. That is fast but not faster than DSD64.

However, with 32 DACs per channel staggered across the sample period we get 24.576 M. That is better than DSD512. For input at or below the native rate of 768K, the DACs operate in parallel. Below the native rate, inserted nulls stretch the output sample period. Above the native rate, the DACs are staggered and the data at each point is the input sample value minus the sum of the data in the other DACs. Thus, each successive sample is the delta needed to reach the next sample point. This approach has interesting repercussions: I will let you ponder them for the time being.
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