Might get a pair. I've got to get my red baron dac working first before I add boutique parts to it.

No.

The tube rectified B+ voltage is ~185VDC with two taps (SSHV input voltage for each channel).

Additionally i have 4 SS rectified voltage lines. 3x ~15VDC and 1x ~25VDC (SSLV input voltage).

Normal isolating tape, for security reasons

so the reference PSU provides 140v for the tubes and ~ 14vdc x2 for the digital circuits?

Neat. What's with the tape on the capacitors?

the pics are currently down in all my blogs. They are all links to the site itself, and probably went down after there upgrade.
I will ask about it.

Unable to see the images. Anything I should do to access?
These were viewable about ten days ago

The PSU PCB is from Jims Audio Store.

Please look if it has still the same GND layout failure!

Cheers,
Oliver

My boards are manufactured from pcbcart.com

If you email the pic to me I'll include it in an edit to the main post.

I drew a pcb for this if anyone is interested. THought I could post it, but apparently pics cannot be added to this section.

Hi there - I notice you are using the Sjostrom rectifiers. What is the PSU PCB you are using? I would like to achieve a similar layout in the F5 I am building with the 2-level design

Thanks, lhalha

Because they slightly varied the test and measurement conditions between the two? Note that the LM1876 graph seems to be a bit more 'realistic', the LM4766 has been 'cleaned up'.

And, different samples? In the characteristics table they're terribly pessimistic about how poor an actual sample can be, a difference of 40dB is allowable -- would be quite easy to get a real "dud"! What could be so variable in the manufacture to make such a difference ...?!

Here's another interesting conundrum - compare and contrast the LM1876 against the LM4766. The schematic has changed in a couple of fairly subtle ways - the upside down current mirror transistor has been corrected, but the other change I've so far noticed is the introduction of an error - a wire crossing at the driver stage is now a connection. I've simmed both and think the LM1876 schematic is correct here. Oh and the output ballast resistors have gone down in value. Nothing else I can see has changed.

But then the positive rail PSRR plots are amazingly different - so what can possibly account for this?

Sounds, as in fact is obviously the case, that getting the accuracy in the model is crucial. Real tests on real sample, and using extremely tightly controlled behaviours of the driving voltage sources, and also done at various loads, will be the only way to get the full story ...

As an addendum to this, I was measuring the distortion of an external sound-card that I recently bought (that uses CS ADC's) and comparing this to my DSP.

I had jigged a couple of DSP's so that I was driving one with a TOSLING cable and using it as a DAC, and using a second DSP with a TOSLINK output back into the computer. Essentially an enormously complex and expensive sound card.

Much to my disgust, my DAC was showing levels of distortion about 10dB higher than the soundcard. DAMN what the....

Mind you, we are talking distortion waaaay down in the -100dBc region.

After several tantrums and several cups of coffee, I worked through an analysis of the issue. Guess what?

THE DISTORTION WAS ALMOST ALL COMING FROM THE PGA2320!

A long hard look at the PGA datasheet shows that this is not inconsistent with it's specs.

A logical think about it says that this level of distortion is so low that I should be happy. But in the end of the day, the very thing I added to make the performance "better" has turned out to be the limiting thing in the design!

That is what you get for "doing too much before you think".

The crystal is 12.288MHz. This is required to run the DSP at 256Fs for a 48KHz sample rate.

It is possible to run this at up to 192KHz - but I just don't see the point. If I did this then there is four times the clock speed and data rate for the A/D and D/A's - which should work but given I do not subscribe to the golden ears credo of "being sensitive to stuff that my ears just can't hear" I have not tried this.

A second effect would be that the delay distance would be correspondingly scaled down. This might be seen a s a benefit - but my experience is that the distance steps of 1/Fs work just fine for time alignment of drivers.

If I were trying to do a high resolution alignment then I think increasing Fs might be useful...

Pressing on with the sim to test my hypothesis - so far all results are from running positive rail PSRR. This is the better one, when I've understood this I'll move on to the negative rail.

Installing a hefty RC on the positive rail which only leaves the two output emitter follower stages (driver & output) exposed to the ripple gives 110dB below 80Hz. This seems too good - I rather suspect the models now, particularly for the output devices. Perhaps these transistors have no output (collector-base) capacitance?

So it looks as if it might not be the output stage, rather the TIS (or VAS) which is the culprit. However protecting only this stage from the ripple while having the input stage exposed gives a very poor plot (power supply gain above a few kHz) so this approach looks invalid. Anyway going back to the detail of the plot - with only the driver and output stages seeing ripple, we have about 61dB PSRR at 20kHz, from the +ve rail. Moving the driver collector to the clean supply, the performance gets amazing (too amazing so the models must be suspect) - 126dB below 1kHz and 107dB at 20kHz.

So rather looks like my 'output stage is the culprit' hypothesis has taken a fatal hit. That is until I verify what the output transistor models really are. Stay tuned.....

OK I am gradually getting the hang of understanding PSRR better, let's see how my explanation goes.

After fixing up the imbalanced current mirror (two resistors in the emitterss - one got changed at some point) now the PSRR in the normal 26dB closed loop gain maxes out at 65dB below 1kHz. This was the anomaly I had been scratching my head over for a few hours. That's because I expected to see it climb as shown in the DS PSRR graph, reaching 103dB minus the closed loop gain of 26dB or about 77dB. But in fact its 12dB short of this.

My understanding of how this discrepancy arises is that those PSRR plots are for the open loop case and are referred to the input. In such a case the input signal is obviously very small, there's very high OL gain at LF. So what dominates the PSRR is the supply rejection of the input stage. This is rather akin to noise figures being dominated by input stage noise in high gain configurations.

However in the CL case with only 26dB of gain the output signal is much smaller and so tthe output stage PSRR can dominate the figure - which is what I think is happening. When feedback is applied the limiting factor is no longer the input stage's PSRR rather the output stage's. The figure of 65dB seems remarkably similar to that achieved by the LME49600 buffer. Obviously that one is output stage limited as its only an output stage

So if this understanding is correct then the usual chip amps do not in fact offer better PSRR at lower freqs (than the TDA8566) as I had previously imagined going by their PSRR plots. Also what follows from this (if its correct) is there's precious little point in filtering the small signal stages (as can be done on the TDA7294 for example) because the damage is being done at the output stage. So this would mean chipamps do not in fact lose out to discrete amps where the small signal stages can be filered to an arbitrarily high level - both are in fact output stage limited in practice.

Yep, sounds interesting ... send it along when you reckon you've got it sorted ...

Thanks,
Frank