Here's a circuit that's been a long time in gestation - some logic that converts I2S from 64fs (32bits per sample) down to 32fs (16bits).
Almost all the S/PDIF receiver chips nowadays output a bit clock at 64fs (2.8MHz for RBCD) because the format has the potential to support up to 24bits. When being driven from a CD player though, there's no chance of any useful information occupying those spare bits. As my interest is to run all signals as slow as possible to keep noise to the absolute minimum, 64fs to me is profligate generation of RF when 32fs will do the job. But only the WM8805 supports this format and then only when software programmed.
The other reason for wanting the slower bit clock is that my LAID design relies on shift registers and the 32fs clock gives me twice as good utilization of the serial storage - no bits are being wasted on zero padding.
This circuit is designed to do the job with the fewest standard logic chips I could manage...