Posted 10th November 2013 at 11:00 AM byrjm Updated 10th November 2013 at 01:11 PM byrjm
Last one for today.
I was having problems getting this to work, the key seems to be adjusting R6 to null the voltage offset. Works fine now, but this is just a rough reverse engineer of the diagram, the parts values and the type of transistors are essentially placeholders.
The input jFET is shown as a dual package. The output bias current is most likely much lower than the 100 mA I configured, so the class A output power is proportionately smaller. For the rest of the currents and the types of transistors used, your guess is as good as mine.
edit: R7 should most likely be closer to 47 ohms, while another 5p capacitor should go in parallel with the feedback resistor, R17.