JFET SRPP RIAA Preamp

Attached is a schematic showing a JFET SRPP RIAA preamp using the PN4303 JFET , which is available form Goldmine Electronics and from Mouser. Distortion was (according to simulation) lower for the 4303 than for higher gain devices like the 2SK170, PN4393, or J110, which was the rationale for chosing a MOR device like the 4303. The 2N5459 might also be suitable for this application, but the breakdown voltage is marginal at 25V. FETs were selected in pairs for equal VGS at 2ma drain current using a homebrew matching jig. The circuitry at the right is a discrete shunt regulator used to knock down a 40V unregulated power supply to +30V. Gain is 38 dB each side at 1kHz into a 20k load, with 0.1dB gain matching between channels. I intend to use this preamp to replace a modified Pacifiic RIAA already used in a test setup in my living room (subject of a previous thread about 6 months ago) The Pacific was (and still is) pretty satisfactory working with a Kenwood KD-2055 turntable with a Grado Gold cartridge. However, the high level distortion (as simulated ) for the SRPP should be better than for the Pacific. I am eager to make the replacement to see if I notice any difference. When I replaced the stock Nikko preamp with my current setup, I immediately noticed the change. I would never go back to the Nikko.

As a side note, yes, I'm aware that Elektor has published an SRPP circuit, but I haven't seen it, as I didn't fork out the money to download it. People who have seen the Elektor circuit are free to comment on the similarities/differences. I will follow with a picture of the completed board when I can charge the batteries for my camera...
 

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Here's a pictrue of the board. The blobs of hot melt are for strain relief. If there is interest, I'll post some pics of the gain-phase plots. Oh yeah, in the current incarnation of this preamp, C9 and C10 are 1uF, not 3uF.
 

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Richard,

Looks really good. But no cap on the output of shunt reg? I'm curious if it sounds better without C12 loading input. Bet the treble is improved. Also, C9 does not have to be that big, though we all understand the reality of having certain parts already in the bin.

What is output impedance? Might have a little trouble driving difficult loads, idling at just 2mA.

jh:)
 
I haven't checked the output impedance yet, but in my simulations, the output stage was definitely happier with a 20k load than with no load in terms of distortion (not surprising with a SRPP). The gain and phase were measured with 20k load using a HP4194A analyzer. I usually like about 40dB gain at 1 kHz for a MM RIAA preamp, but 38 dB was not too far off the money. The RIAA preamp will be driving a 20k pot - not too challenging a load. There is a unity gain line amp in my test preamp box between the pot and the outputs that go out to the cold, cruel world. That one has a much higher idle current (~10ma or so). As for C9 and C10 - the 1M resistors folllowing C9 and C10 are part of the RIAA equalization, like it or not, so I wanted the capacitive reactance of C9 and C10 very much out of the way at low frequency. I also had the caps in my parts bin - Roederstein MKP1839s. (I wish I had more of them). The input capacitors in the schematic are place holders. I'll have to figure out what works best with my Grado Gold. Since it has about 1/10 the inductance and lower resistance than the average MM cartridge, load capacitance doesn't have such a big effect.
Oh yeah - there are some 1uF bypass caps on the 30V rails that aren't shown in the schematic. If I have a little time, I can run a gain phase plot on the regulator before I plunk the whole mess in the box. I was so happy to get the gain equal between channels Friday evening that I carted the preamp home right away with the intention of trying it out .
 
Well, I replaced the modified Pacific that resided in my preamp test bed for about 8 months with the SRPP and it's - different. I'll have to wait 'til I get a good night's sleep so I can do more critical listening, but I would preliminarily call it a bit more "delicate" in its treatment of classical music. There is no residual noise coming from the preamp at normal listening levels, despite the use of cheap "MOR" grade JFETs in its construction. A tentative thumbs up so far.
 
From the way this preamp sounds, I'll have to improve my speakers before I can take its full measure. It handled Muhal Richard Abram's "View from Within" LP with aplomb,with its wide range of honks, blurts, delicate hand-struck pecussion and crisp vibes. The clarinet in the London Stereo Treasury recording of the Mozart Clarinet concerto may also be sounding a bit more true to life. It sounds like I ought to look at borrowing a better pair of speakers for auditioning this thing, as I won't be building new ones in a hurry.
 
Attached is the revised (more complete) circuit, showing all gate stopper resistors and +30V bypass caps. The load resistors at the inputs are currently 47.5k, but will be changed to 16.2k, based on simulation of the resonance of the cartridge inductance with the stray and lumped load capacitance. Simulation shows that this is sufficient damping to get rid of a catridge resonance near 100kHz. The Grado Gold has an inductance of 45 millihenries and a resistance of about 475 ohms, which accounts fror the HF resonant peak.
 

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The attached schematics show basic gain cell circuit topologies I've tried or am planning to try. All are simple circuits using only N-channel JFETs with no global feedback. Circuit 1 is a simple common source amplifier with cascode loading driving a source follower output stage for low output impedance. This circuit was described in a thread called "open loop follies pt.1" from a few months ago.

Circuit 2 shows the SRPP gain cell used in the preamp described in this thread. The parts count is much lower, and you get gain and reasonably low output impedance for driving a passive RIAA network or volume pot. The SRPP also allows one to use non-exotic JFETs and get pretty reasonable results. I'll be living with this circuit for a while, and then go to circuit (3).

Circuit (3) is very similar to (1), except for the addition of a JFET current source dumping into the gain FET (Q1). The rationale behind this attempt is to be able to use a high IDSS JFET like the J110 and still be able to simultaneously program a reasonable gain and center the drain voltage near 1/2 the supply voltage for optimum dynamic range. Running the gain FET at high idle current is also meant to reduce the distortion at high signal levels, like in the second stage of a passive equalized RIAA preamp. The simualtions of this circuit look promising, though the SRPP may have lower distortion with fewer parts. Even if this is the case, I'll go ahead and try (3) just to see if it has a different sonic palette.

This all started because I was very curious as to how a simple open loop (no global feedback) preamp would sound. Answer - pretty *&##@%$ good. Also, I was a bit annoyed with some pundits in another thread (actually, one i particular) that insisted you needed an exotic high-gm Japanese JFET for decent sound. I started in (1) with the 2SK170, one of those exotic FETs, then designed it out of the circuit to see what sort of performance could be had with "proletarian" part types readily available in the U.S. I'm pretty pleased so far with the sound of an SRPP circuit using a humble PN4303. Circuit (3) is all built up and ready to go. I'll try it and describe the results in another thread after I've lived with the SRPP preamp for a few months.
This is the last I will post on this thread unless someone else has some comments or questions.
 

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I like circuit #1, think it will sound better than #2. I bet #1 has lower distortion, #2 with plenty of good 2nd order, but maybe too much.

Not sure if #3 will work. The cascode works by feeding the upper transistor with a current source (signal). In this case, you've taken the current away with the extra fet. Won't this remove dc bias current from output? Could go very nonlinear.

jh:)
 
(1) is the circuit I previously had in my preamp test bed. The tother thread I cited talks about it. It has higher distortion at high levels than (2), at least, according to PSPICE simulation, which han't steered me wrong so far with simple circuits like these. This is the reason I was eager to try the SRPP, along with the challenge of getting one to work. At low levels they are about equal in THD. Simulated harmonic distributions are also similar, being overwhelmingly 2nd order, with just a touch of 3rd order. I've measured the distortion of (1) with an Audio Precision analyzer, and it is reasoably close to what is predicted by the PSPICE simulation. I can't say whether one circuit sounds better than the other, as it is early days yet - they are certainly a bit different.

The current source feeding the bottom FET in (3) doesn't take anything away from the signal, as the bottom FET has its drain voltage pinned by the cascode above it. What the extra FET gives you is an extra degree of freedom in choosing the bias current of the bottom FET, as now not all the bottom FET bias current is running through the load resistor. The circuit simulates well and has a simulated high level THD about 1/2 that of (1).
 
Attached is a picture of a simulation of circuit 3. Gain is about 35 for the part values shown, just a little more than what I would use fior the 2nd stage of a passively equalized RIAA preamp for MM voltage levels. Distortion at about 1.4V output (40mV input) driving 10k is 0.19% at 10kHz, with 2nd harmonic overwhelminly predominant (3rd is 40 dB down from 2nd). Low level distortion with 1mV drive is 0.008%. Circuit (1) delivers about 0.4% distortion at the same high output level.
 

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Attached is a simulation of the SRPP circuit using PN4303 with distortion results attached. You can see immediately why I was compelled to try this one out. Even if the actual THD was 10X the simulation, it would still be lots better than either of the common source amplifier-based circuits shown in (1) and (3) a couple of posts ago.
To select FETs, I tested for Vgs at 2ma drain current and looked for a Vgs grouping to emerge. I found a population of FETs that had a Vgs of about 1.2V at 2ma drain current and paired FETs that were matched to within 0.005V Vgs. This is also how I arrived at the 604 ohm value for source resistors shown in the final schematic., and why this value is different from the one used in the simulation. I'm thinking of changing to 402 ohms to boost the quiescent current to 3ma to seee it anything hapens to the sonic characteristic, but not until I have a lot more listening time under my belt....
 

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I'm not familiar with the Aikido circuit. I'll try having a look at it, but for the present, I'm limiting the evaluation to the topologies I've already listed, as I only have so much time to build up and evaluate things.
Since the preamp is only required to drive a volume pot, output impedance is not a prime concern. As I explained earlier in this thread, I have a source follower line amplifier in my test box that takes care of the interface to the outside world. I'll eventually be messig with that, too, but that's a subject for another thread.
 
I've looked at the Aikido circuit, and did a JFET simulation using PN4303 in the first stage and PN4393 in the second stage. The THD was about 0.01% with decent harmonic distribution for a gain of 4 (line amp duty). I would consider using it some day in a gain cell for an RIAA amp, except that it uses negative feedback, and I'm limiting myself for the time being to circuits without any global feedback. I probably won't consider it for line amp any time soon either, as it is inverting, and I want to keep my preamp non-inverting overall.
 
I did some more simulations of the Aikido circuit. It is simply a current source loaded common cathode amplifier with a cathode folower output. Its JFET implementation has too much gain to be used in a line ampliifier application without some negative feedback to tone it down, even using cheap low transconductance JFETs. I will try once more using a J201 front end, though, to see what happens. The gain would be ok for a Pacific-type preamp if the front end FETs are carefully selected. High level and low level distortion levels and harmonic distribution are similar to the other two common source amps shown here. The distortion is about 0.1% at high level output (~ 1V out) using PN4303 input FETs throttled down with 499 ohm source resistors, though the gain is a little to high. (~50) for second stage duty in a passive equalized RIAA preamp for MM cartridges. Harmonics were totally dominated by secod order. That's all I'll say about the Aikido. Maybe I'lll try an Aikido/Pacific type RIAA preamp some time down the line when I have a little more time.
 
I was doing some thinking last night, which led to some simulation. The simulation results inducate that one should not be using an SRPP as the front end of a passively equalized RIAA amp. First off, impedance test tend to indicate an output impedance of about 3.6k, which is uncomfortably high to be driving a passive RIAA network and get any accuracy. I will check this again, but it's the value I got with the simulation last night by loading up the output with a capacitor coupled load until the output voltage dropped to 1/2.

What's more disturbing is that the gain is a function of load (no real surprise in retrospect), so that the gain of the SRPP stage changes as the impedance of the equalization network changes, further throwing the RIAA accuracy out of whack. Attached is the test circuit shown for the simulation. Note that there is a probe directly at the output of the SRPP and one at the first capacitor of the RIAA network. In a perfect world, the gain at the output of the SRPP would be constant with frequency - unfortunately, it ain't so...
 

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This next probe shows the results of a frequency response scan. Note that the direct output of the SRPP (the green line) changes fairly radically with frequency, shelving at about 1/2 of its low frequency value.
As a result, I may try some sort of a hybrid approach for my next RIAA circuit, using some variant of a buffered common source amp at the input, with perhaps an SRPP for the output section, depending on whether I can make some changes to lower the output impedance without making the gain go berserk. More later....
 

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