JFET SRPP RIAA Preamp

I've been honing simulations of the gain blocks for this project, and have achieved around 0.0016% THD in simulation on the 40X input gain block using the TIS75 jfet - I bought a few thousand of them at a bargain price from BG Micro while they were still around. This fet has been cited as a relatively low-noise device in some 70's papers on preamps for nuclear measurements,. The gm is similar to that of my other favorite jfet, the PN4393. Both have low input capacitance. When I find my boards, I'll try populating the new version of this preamp to check out how it sounds with a cap-load finnicky AT440 cartridge. Most of the gains in THD performance were attained by tweaking the bias current and the capacitively coupled output load.
 
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Ha - one reason I can't find the boards for the current version of this project is that I never sent out for them in the first place (palm slaps brow...). I'm currently busy turning around the jfets on the board to accommodate the TIS75, as its pinout is reversed as compared to the std D-S-G used by the J112 and PN4393.
 
Just as a teaser, here's the sim schematic and THD sim.
 

Attachments

  • TIS75_SRPP_40X.png
    TIS75_SRPP_40X.png
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  • TIS75_SRPP_40X_THD.png
    TIS75_SRPP_40X_THD.png
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Board population is proceeding. The shunt regulator is populated and working satisfactorily., and almost all caps are in place, except for some NPO compensation caps (line stage) I'll need to run out and purchase. The line amp will be a tried-and-true feedback-based non-inverting design. As a foretaste of things to come, below are the sim results for the line stage... This weekend, I'll be spending some time with my matching jig to select TIS75 fets for the first stage and the line stage. I may use LS189 fets for the second stage.
 

Attachments

  • SRPP_LINE_SCH.png
    SRPP_LINE_SCH.png
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  • SRPP_LINE_OUT.png
    SRPP_LINE_OUT.png
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  • SRPP_LINE_DIST.png
    SRPP_LINE_DIST.png
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