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Old 16th September 2005, 04:23 AM   #11
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(1) is the circuit I previously had in my preamp test bed. The tother thread I cited talks about it. It has higher distortion at high levels than (2), at least, according to PSPICE simulation, which han't steered me wrong so far with simple circuits like these. This is the reason I was eager to try the SRPP, along with the challenge of getting one to work. At low levels they are about equal in THD. Simulated harmonic distributions are also similar, being overwhelmingly 2nd order, with just a touch of 3rd order. I've measured the distortion of (1) with an Audio Precision analyzer, and it is reasoably close to what is predicted by the PSPICE simulation. I can't say whether one circuit sounds better than the other, as it is early days yet - they are certainly a bit different.

The current source feeding the bottom FET in (3) doesn't take anything away from the signal, as the bottom FET has its drain voltage pinned by the cascode above it. What the extra FET gives you is an extra degree of freedom in choosing the bias current of the bottom FET, as now not all the bottom FET bias current is running through the load resistor. The circuit simulates well and has a simulated high level THD about 1/2 that of (1).
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Old 16th September 2005, 05:52 AM   #12
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Attached is a picture of a simulation of circuit 3. Gain is about 35 for the part values shown, just a little more than what I would use fior the 2nd stage of a passively equalized RIAA preamp for MM voltage levels. Distortion at about 1.4V output (40mV input) driving 10k is 0.19% at 10kHz, with 2nd harmonic overwhelminly predominant (3rd is 40 dB down from 2nd). Low level distortion with 1mV drive is 0.008%. Circuit (1) delivers about 0.4% distortion at the same high output level.
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Old 17th September 2005, 03:10 AM   #13
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Attached is a simulation of the SRPP circuit using PN4303 with distortion results attached. You can see immediately why I was compelled to try this one out. Even if the actual THD was 10X the simulation, it would still be lots better than either of the common source amplifier-based circuits shown in (1) and (3) a couple of posts ago.
To select FETs, I tested for Vgs at 2ma drain current and looked for a Vgs grouping to emerge. I found a population of FETs that had a Vgs of about 1.2V at 2ma drain current and paired FETs that were matched to within 0.005V Vgs. This is also how I arrived at the 604 ohm value for source resistors shown in the final schematic., and why this value is different from the one used in the simulation. I'm thinking of changing to 402 ohms to boost the quiescent current to 3ma to seee it anything hapens to the sonic characteristic, but not until I have a lot more listening time under my belt....
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Old 17th September 2005, 04:19 AM   #14
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Why not try the Aikido circuit with jfets for a lower output impedance?
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Old 17th September 2005, 04:28 AM   #15
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I'm not familiar with the Aikido circuit. I'll try having a look at it, but for the present, I'm limiting the evaluation to the topologies I've already listed, as I only have so much time to build up and evaluate things.
Since the preamp is only required to drive a volume pot, output impedance is not a prime concern. As I explained earlier in this thread, I have a source follower line amplifier in my test box that takes care of the interface to the outside world. I'll eventually be messig with that, too, but that's a subject for another thread.
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Old 17th September 2005, 05:39 AM   #16
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I've looked at the Aikido circuit, and did a JFET simulation using PN4303 in the first stage and PN4393 in the second stage. The THD was about 0.01% with decent harmonic distribution for a gain of 4 (line amp duty). I would consider using it some day in a gain cell for an RIAA amp, except that it uses negative feedback, and I'm limiting myself for the time being to circuits without any global feedback. I probably won't consider it for line amp any time soon either, as it is inverting, and I want to keep my preamp non-inverting overall.
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Old 18th September 2005, 01:02 AM   #17
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I did some more simulations of the Aikido circuit. It is simply a current source loaded common cathode amplifier with a cathode folower output. Its JFET implementation has too much gain to be used in a line ampliifier application without some negative feedback to tone it down, even using cheap low transconductance JFETs. I will try once more using a J201 front end, though, to see what happens. The gain would be ok for a Pacific-type preamp if the front end FETs are carefully selected. High level and low level distortion levels and harmonic distribution are similar to the other two common source amps shown here. The distortion is about 0.1% at high level output (~ 1V out) using PN4303 input FETs throttled down with 499 ohm source resistors, though the gain is a little to high. (~50) for second stage duty in a passive equalized RIAA preamp for MM cartridges. Harmonics were totally dominated by secod order. That's all I'll say about the Aikido. Maybe I'lll try an Aikido/Pacific type RIAA preamp some time down the line when I have a little more time.
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Old 21st October 2005, 05:04 AM   #18
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I was doing some thinking last night, which led to some simulation. The simulation results inducate that one should not be using an SRPP as the front end of a passively equalized RIAA amp. First off, impedance test tend to indicate an output impedance of about 3.6k, which is uncomfortably high to be driving a passive RIAA network and get any accuracy. I will check this again, but it's the value I got with the simulation last night by loading up the output with a capacitor coupled load until the output voltage dropped to 1/2.

What's more disturbing is that the gain is a function of load (no real surprise in retrospect), so that the gain of the SRPP stage changes as the impedance of the equalization network changes, further throwing the RIAA accuracy out of whack. Attached is the test circuit shown for the simulation. Note that there is a probe directly at the output of the SRPP and one at the first capacitor of the RIAA network. In a perfect world, the gain at the output of the SRPP would be constant with frequency - unfortunately, it ain't so...
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Old 21st October 2005, 05:10 AM   #19
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This next probe shows the results of a frequency response scan. Note that the direct output of the SRPP (the green line) changes fairly radically with frequency, shelving at about 1/2 of its low frequency value.
As a result, I may try some sort of a hybrid approach for my next RIAA circuit, using some variant of a buffered common source amp at the input, with perhaps an SRPP for the output section, depending on whether I can make some changes to lower the output impedance without making the gain go berserk. More later....
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Old 21st October 2005, 06:48 AM   #20
steenoe is offline steenoe  Denmark
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Impressive work The idea of using an available JFET is
pretty cool. Looking forward to see the final result of your tests.

Steen
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