Werner said:
Hi Werner,
verified !
in the datasheet, it says that the top of the aluminium case has a drain marker, and when looking at what is inside (just two normal TO92 JFETS, mounted back to back) it is clear they must be interchangeable ...
well, the 2SK240 is exactly a double 2SK170, and has the same data.
regards,
Hartmut
Dear Werner, I am always happy to help.
Turn the device over, so that you are looking at the bottom (pin side). From left to right, top row: drain 1, gate 1, source 1.
From left to right, bottom row: drain 2, gate 2, source 2.
This is from the yearly FET data book published by CQ Shuppan, which is something of a Japanese industry standard.
>D and S are mostly interchangeable.<
It appears that Toshiba thinks so, too. The 2SK240 was one of those Toshiba oddities in which, instead of putting two wafers into a hermetic can, they simply took two identical TO-92 plastic devices and put them into an aluminum can, with the flat surfaces touching. If the two TO-92 devices were identical, you would _expect_ that the pin orientation would be drain 1, gate 1, source 1, source 2, gate 2, drain 2. But no, the drains and sources exit together. So either the two TO-92 devices are _not_ identical, or the differences between source and drain don't matter very much on these Toshiba JFETs.
I wonder how many other dual JFETs this is true for (even if the manufacturer doesn't say so). Because if so, it would certainly make it easier to create PCB layouts for differential amp stages. Anyone tried this for, say, the Vishay-Siliconix 2N5564~5566 family?
regards, jonathan carr
Turn the device over, so that you are looking at the bottom (pin side). From left to right, top row: drain 1, gate 1, source 1.
From left to right, bottom row: drain 2, gate 2, source 2.
This is from the yearly FET data book published by CQ Shuppan, which is something of a Japanese industry standard.
>D and S are mostly interchangeable.<
It appears that Toshiba thinks so, too. The 2SK240 was one of those Toshiba oddities in which, instead of putting two wafers into a hermetic can, they simply took two identical TO-92 plastic devices and put them into an aluminum can, with the flat surfaces touching. If the two TO-92 devices were identical, you would _expect_ that the pin orientation would be drain 1, gate 1, source 1, source 2, gate 2, drain 2. But no, the drains and sources exit together. So either the two TO-92 devices are _not_ identical, or the differences between source and drain don't matter very much on these Toshiba JFETs.
I wonder how many other dual JFETs this is true for (even if the manufacturer doesn't say so). Because if so, it would certainly make it easier to create PCB layouts for differential amp stages. Anyone tried this for, say, the Vishay-Siliconix 2N5564~5566 family?
regards, jonathan carr
Proper use of lead-batteries
Hi again,
I'm up and about to give my circuit a proper housing and all.
How do I treat the lead acid batteries right? They spend a voltage of +24V, and at the moment I'm feeding them through a simple PSU mainly constisting of a L200 current+voltage regulator wich provides 26,4 V. Normally, i don't disconnect batteries from PSU while listening. Is this the way to go? Or should I charge batteries with 27,6V and disconnect, when charged? Or design a tricky circuit that dis- and reconnects depending on state of batterie?
Advice is very appreciated,
Rudiger
Hi again,
I'm up and about to give my circuit a proper housing and all.
How do I treat the lead acid batteries right? They spend a voltage of +24V, and at the moment I'm feeding them through a simple PSU mainly constisting of a L200 current+voltage regulator wich provides 26,4 V. Normally, i don't disconnect batteries from PSU while listening. Is this the way to go? Or should I charge batteries with 27,6V and disconnect, when charged? Or design a tricky circuit that dis- and reconnects depending on state of batterie?
Advice is very appreciated,
Rudiger
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