RIAA 75uS on first stage - diyAudio
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Old 8th July 2014, 08:19 PM   #1
BigE is offline BigE  Canada
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Default RIAA 75uS on first stage

Hi there!

Here is an LTspice schematic of my proposed first stage. I am concerned about noise with MC cartridges....

LT spice does not seem to lower the noise figure when more jfets are added to the first stage, and the noise seems rather high, at around 110 uV. Using an op amp with feedback results in much much lower noise ( 1.6 uV ).

Is this solely due to the feedback? Can I acheive op amp levels of noise with jfets?

Thanks for your help!

Cheers!
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File Type: asc Parallel front end with 75uS time constant.asc (1.7 KB, 24 views)
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Old 8th July 2014, 09:56 PM   #2
BigE is offline BigE  Canada
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Adding a little feedback (30k between output and gate) reduced the noise a little,but only by 10 uV. It also tightened up the RIAA response in the main circuit and helped with the phase.....
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Old 8th July 2014, 10:07 PM   #3
BigE is offline BigE  Canada
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Sorry to bother.... testing noise from that section alone gives 1.3 uV.... That is not where the noise is coming from.....

Thanks!
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Old 8th July 2014, 10:18 PM   #4
SY is offline SY  United States
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Could you please post an image of the schematic for us benighted souls who can't read asc files?
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Old 8th July 2014, 11:49 PM   #5
BigE is offline BigE  Canada
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Can LTspice make pdf files? Here is a png via paint. I'm sure there is much wrong with this. It is my first ever circuit design. BTW: LTspice noise analysis does show a drop off in noise as the jfets were added. I was using it wrong...
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File Type: png RIAA front end.png (30.2 KB, 96 views)

Last edited by BigE; 8th July 2014 at 11:52 PM.
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Old 9th July 2014, 07:22 AM   #6
Calvin is offline Calvin  Germany
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Hi,

attached is a changed file.

If the filter in the frontend should work at all it requires a series impedance it can work upon.
In the file the signal voltage sources therefore got a series resistance value of 1R.
Set it back to 0 and see the difference (for 75 choose appropriate values).

Then, the dimensioning of the circuit is completely off.
- The JFETs are almost fully cut off.
- The negative supply is not necessary, thanks to JFETs beeing depletion mode (normally on) devices and as long as the input voltage remains lower than the Vgs value.
- The Source resistor directly affects noise. The larger the more noise. So keep Rs as small as possible.
- The Drain resistor also affects noise- just on a smaller scale than Rs. Try to keep it as small as possible also. This requires to run the JFETs with considerable drain current.
- Choose rather high drain current values. Besides lowering voltage noise JFETs improve sonically when running a bit hot.

In the modded file the single-supply, lowohmic , high-Bias version´s noise figure is 16dB lower.

jauu
Calvin
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File Type: asc Parallel front end with 75uS time constant.asc (5.9 KB, 8 views)

Last edited by Calvin; 9th July 2014 at 07:31 AM.
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Old 9th July 2014, 03:30 PM   #7
BigE is offline BigE  Canada
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Wow! That is much more than I expected THANK YOU!

I was not sure how to set the values of Rsand Rd...

By saying that the jfets were nearly cut off, that means they were not working in saturation mode? Sorry for the newbie question, it's a little difficult picking this up just with googled info.

This site is invaluable for gems such as this!

Cheers!
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Old Yesterday, 03:05 AM   #8
BigE is offline BigE  Canada
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Am I right to assume that if the DC operating point of the bypass cap to ground simulates as 3 volts, then a 6.3 volt cap is fine?
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Old Yesterday, 10:57 AM   #9
oshifis is offline oshifis  Hungary
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I would select the voltage rate higher than V1. Also is the value of R1 correct? 1M seems to high as a source resistor.
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Old Yesterday, 11:51 AM   #10
BigE is offline BigE  Canada
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Thank you for your response!

I chose 18V because this is going into an existing circuit. The 1M source resistor is changed to 150 ohms, and the drain resistor is changed to 470 ohms as per Calvin's suggestion.
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