Having followed with interest Salas's "Simplistic" thread, I am interested in getting feedback on improvements I could make to my battery-powered, JFET-based 'Muse' phono stage.
This started off as the MM "Le Pacific" circuit published in a late-80s 'Silicon Chip'magazine ... but after several revamps has turned into quite a different circuit (also different to the Simplistic! 😀 ) with, for v4, 58dB of gain. Each version has sounded better than the previous versions (which I have sold off to friends) but I'm interested to see if it can be made to sound even better. 😉 (v4 was compared to a Brinkman 'Edison' and, sure, it wasn't as good ... but not by much! 😀 )
I have attempted to model it in LTSpice, to get an idea of the distortion profile - but haven't been able to get very far.
Anyway, attached is the circuit.
Regards,
Andy
This started off as the MM "Le Pacific" circuit published in a late-80s 'Silicon Chip'magazine ... but after several revamps has turned into quite a different circuit (also different to the Simplistic! 😀 ) with, for v4, 58dB of gain. Each version has sounded better than the previous versions (which I have sold off to friends) but I'm interested to see if it can be made to sound even better. 😉 (v4 was compared to a Brinkman 'Edison' and, sure, it wasn't as good ... but not by much! 😀 )
I have attempted to model it in LTSpice, to get an idea of the distortion profile - but haven't been able to get very far.
Anyway, attached is the circuit.
Regards,
Andy
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I have some comments/suggestions (combined with simulations), but they'll wait until I'm more awake. Given the paralleled jfets, was this meant for an MC cartridge?
Thank you, wrenchone - I look forward to hearing them.
AIUI, paralleled JFETs deliver:
1. increased gain, and
2. lower noise.
(I seem to remember the Pass 'Pearl' had 4 FJETs in its first gain stage?)
But, yes, I wanted to have sufficient gain for my LOMC. 🙂 Earlier versions of the circuit (with different JFETs) were only suitable for an MM.
The circuit shown delivers 58dB gain (4,000mV out from 5mV in). By reducing the 1st stage gain resistor to 750 ohms, I made a second pair of boards which deliver half that (2,000mV out from 5mV in) - which I can use with my Grado RR1.
First listen is tomorrow. 😀 (I've been running it in for the last 3 weeks by playing my FM tuner through it, via a Hagtech reverse RIAA board, during the day and charging overnight.)
Regards,
Andy
Normally, butting one current source (a jfet) against another is not a good idea. In this case, the gain resistor acts as a"pressure relief valve" and yields a practically realizable circuit. The concept is interesting. A few comments:
1) The combined impedance of the input jfets and bipolar current source will be considerably smaller than 50M, more in the region of a few 10s of k, and dominated by the bipolar current source. I took a peek at the data sheet for the 2SA1142, and there is no data for the hoe, but this should be pretty low anyway, as the transistor is supplying no less than 4 fets - the output impedance of a transistor generally goes down with increasing collector current. However, this is the sort of error that can be trimmed out by testing with an inverse RIAA network and adjusting the load resistor. The error can also be reduced by cascoding the input fets and current source.
2) The Pearl preamp used 4 paralleled jfets for lower noise, but it also cascoded those fets to avoid the cumulative effects of the Miller capacitance.The Grado cartridge you mention using, if it is like the other products in their line, is a moving iron design with relatively low inductance, and a tolerance of a wide range of capacitive loading. Other moving magnets cartridges are less tolerant, and the cumulative capacitance may make it impossible to properly tune a less tolerant cartridge. Cascoding at least removes the Miller capacitance from consideration. Depending on your operating drain voltage, cascoding the input jfets is also a good idea as you can keep the drain voltage below the point at which gate leakage takes off exponentially. At 8V VDS, the 2SK170 is already in this exponential gate leakage region (it shows up in the specs), probably due to the large area gate required for its high gain, low noise specs.
3) The Pearl and Pearl II circuits use individual source resistors for the paralleled fets - a good idea, as it evens out any residual mismatch between devices, even if it does add a little noise. I noticed that the paralleled fets don't have any gate stoppers, a situation that may invite oscillation - if you don't use gate stoppers, you should at least check for oscillation with a scope or by using an AM radio as a sniffer. The Pearl and Pearl II circuits appear to get away without using gate stoppers, but I'd still check.
4) Using all those fets for low noise and then using a relatively high impedance RIAA network ? You have the possibility of rearranging the circuit to place the RIAA network directly across the gain resistor, as it is being fed by two current sources anyway (R1 goes away). I've used this scheme with a folded cascode stage, and it works. Given the value of your load resistor, the capacitor values would be somewhat enormous, but this serves to help swamp out the effect of strays. It's something to think about, anyway.
If I have time, I'll try simulating one of the gain stages later today - I'm curious about the results.
1) The combined impedance of the input jfets and bipolar current source will be considerably smaller than 50M, more in the region of a few 10s of k, and dominated by the bipolar current source. I took a peek at the data sheet for the 2SA1142, and there is no data for the hoe, but this should be pretty low anyway, as the transistor is supplying no less than 4 fets - the output impedance of a transistor generally goes down with increasing collector current. However, this is the sort of error that can be trimmed out by testing with an inverse RIAA network and adjusting the load resistor. The error can also be reduced by cascoding the input fets and current source.
2) The Pearl preamp used 4 paralleled jfets for lower noise, but it also cascoded those fets to avoid the cumulative effects of the Miller capacitance.The Grado cartridge you mention using, if it is like the other products in their line, is a moving iron design with relatively low inductance, and a tolerance of a wide range of capacitive loading. Other moving magnets cartridges are less tolerant, and the cumulative capacitance may make it impossible to properly tune a less tolerant cartridge. Cascoding at least removes the Miller capacitance from consideration. Depending on your operating drain voltage, cascoding the input jfets is also a good idea as you can keep the drain voltage below the point at which gate leakage takes off exponentially. At 8V VDS, the 2SK170 is already in this exponential gate leakage region (it shows up in the specs), probably due to the large area gate required for its high gain, low noise specs.
3) The Pearl and Pearl II circuits use individual source resistors for the paralleled fets - a good idea, as it evens out any residual mismatch between devices, even if it does add a little noise. I noticed that the paralleled fets don't have any gate stoppers, a situation that may invite oscillation - if you don't use gate stoppers, you should at least check for oscillation with a scope or by using an AM radio as a sniffer. The Pearl and Pearl II circuits appear to get away without using gate stoppers, but I'd still check.
4) Using all those fets for low noise and then using a relatively high impedance RIAA network ? You have the possibility of rearranging the circuit to place the RIAA network directly across the gain resistor, as it is being fed by two current sources anyway (R1 goes away). I've used this scheme with a folded cascode stage, and it works. Given the value of your load resistor, the capacitor values would be somewhat enormous, but this serves to help swamp out the effect of strays. It's something to think about, anyway.
If I have time, I'll try simulating one of the gain stages later today - I'm curious about the results.
Thanks very much for taking the time, wrenchone - I look forward to your next comments. 🙂
Adding a CCS to each JFET gain stage was suggested by the late great Allen Wright, when I sent him the original circuit for comment. He said this would lower distortion.
Aah, I did not know that the CCS would reduce the Zin of the JFETs to a few 10s of Kohms - thanks. Is there any way to increase it back up to, say 1 or 2 Meg?
I'm thinking the outcome of the present circuit is as follows:
* on the 1st gain stage, this low Zin will be combining with the 47K "cart load" resistor to deliver something a lot lower than 47K to the cart? So I really should increase the 47K to, say, 100K?
* on the 2nd gain stage, the low Zin will reduce the 806K R0 to something much lower ... so the 2nd gain stage will not be loading the 1st gain stage optimally? So I should increase R0 ... which will of course change the RIAA values.
The current going through the 2SA1142 is about 28ma. The 1st gain stage deliberately has a fixed Gain resistor (as this sets Zout and so affects the RIAA calculation); what I do when setting up the values of the pots is:
* adjust the Source res so the current flowing through the JFETs is around 80% Idss (so 20.4ma for these 4 JFETs).
* then adjust the CCS res so the Drain voltage is half supply.
I'd be grateful if you would explain what "cascoding the input jfets and current source" involves. I have heard of the term "cascoding" but I don't know how to set this up. 😱
Miller capacitance in the 2nd gain stage certainly delivers a "problem" as it:
a) depends on the gain of that stage, and
b) adds to the value of C2 (so I have to decrease C2 by the estimated Miller capacitance - typically 30pF x 60 gain - to get back to the theoretical RIAA value).
But what "problem" does the Miller capacitance of my 1st gain stage generate?
Again, if you can tell me what "cascoding" involves, I will do it. 🙂
What are "gate stoppers"?
I did get oscillation in v2 of the circuit (I could see it on my 'scope) - which I was able to cure by putting the 100pF cap across the input.
The original Silicon Chip circuit is attached below. That was my v1 ... I simply kept making changes which various luminaries suggested, over 4 years - and listened to the result - to arrive at the current v4 circuit.
As you can see, it had a passive composite RIAA network between 2 gain stages ... so I simply kept with this concept (and it's one favoured by the "valve guys"! 😉 ).
I would be most interested in how to "place the RIAA network directly across the gain resistor (removing R1)".
Thanks,
Andy
Until I get back to this, I would suggest doing a little homework on cascode circuits. Start by searching inside the Simplistic thread started by Salas, and then by doing a search on the web in general. This should answer a few questions, and maybe generate a few more. Nelson Pass in particular had a nice little article on cascode circuits that appeared in Audio magazine in the late 70's. I found it quite illuminating back then. A search for "Nelson Pass cascode" might dig up that article.
Here is a simulation of this topology using a single jfet, with both the jfet and current source cascoded. I tweaked the gain to a value I'd use for a MM RIAA input stage, 40X. The THD is similar to that seen for a simple cascoded jfet common source amplifier, and is higher than that seen for the simulations I've done for a folded cascode RIAA input stage. The THD looks ok, but what I find a little disturbing is that the higher order odd harmonics (3rd, 5th, 7th) are pretty constant in amplitude, even though they are fairly decently suppressed as compared to the 2nd harmonic contribution. This might be remedied with more tweaking, but maybe not as well. When I have some more time, I'll look at the basic circuit without cascoding, though I expect that the THD will be similar to the cascoded version.
Attachments
Hi wrenchone,
After quite some study of this in the past 10 weeks or so, I'm afraid I still cannot reconcile the circuit you simulated against my circuit? It seems to me to be completely different ... so what relevance does its distortion profile have to mine? 😕
In an earlier post, you said:
2) The Pearl preamp used 4 paralleled jfets for lower noise, but it also cascoded those fets to avoid the cumulative effects of the Miller capacitance.
Now, I can understand your point about cumulative Miller capacitance being a baad thing for mm carts. So if "Cascoding at least removes the Miller capacitance from consideration" ... then I would like to know how to cascode those 4 FETs in my 1st gain stage. (I've searched the Web for cascodes - including trying to find the Nelson Pass article you alluded to - but I can't find anything that I can understand. 😱 )
And you commented "I noticed that the paralleled fets don't have any gate stoppers, a situation that may invite oscillation". I certainly didn't notice any oscillation when I tested it before assembling it into the case - and subsequently listening to it - but, strangely enough, a subsequent audition at a friend of mine suggested that we heard oscillation (and when I took it home and put the 'scope on it, I could see multiple dancing sine waves - which tell me that it is unstable).
So I am about to take it apart to install 100 ohm Gate stoppers. 🙂
And WRT "You have the possibility of rearranging the circuit to place the RIAA network directly across the 1K54 gain resistor (R1 goes away)".
Do you mean leaving the 2 x RIAA "legs" as they are but simply removing R1 (47K)?
I thought an essential design criteria for this "passive RIAA sandwiched between 2 JFET gain stages" was that the Zout of the 1st gain stage (which is 1K54) needs to be 1/20th to 1/30th of the following impedance. With R1 there (47K), this requirement is satisfied ... without R1, surely it is not?
Thanks,
Andy
Flail around by yourself., or learn basic electronics. LT Spice is a good tool - download it and learn to use it. My efforts here are wasted, and I'm unsubscribing from this thread.
If you have unsubscribed, you may not read this ... but let me assure you, wrenchone, your input to this thread was not wasted. 🙂
If you believe DIYAudio is all about experts interacting with other ... then IMO you have a narrow view of it. Many others here provide assistance to those less endowed with technical knowledge - Nelson Pass and Mark Kelly for example.
Regards,
Andy
If you were looking for someone to spoon-feed the basics from ground up without any effort on your part, you'll be looking for quite a while. Even Nelson is not that generous.Did you even bother to do a Google search for cascode?
Actually, yes I did, wrenchone - but what I found didn't increase my store of knowledge. 😱
I also spent a couple of fruitless hours on several occasions trying to create a circuit in LTSpice - without any success. So I am looking for someone local who can tutor me "at screen".
Regards,
Andy
Let me be blunt and to the point. The fact that no one but me has responded to your post so far should tell you something. I was a fool for chiming in. If you can't learn from the huge amount of data on cascode circuits on the web, I certainly can't help you. My time is better spent (and it's mostly borrowed and stolen) working on my own projects and circuits. Goodbye.
to wrenchone:
what a juvenile response.
shame on you.
if you don't want to help just stay quiet, there is no need to behave like this.
with one stupid remark you defeat all the good that you did before.
a decent person would apologize but I'm not holding my breath.
what a juvenile response.
shame on you.
if you don't want to help just stay quiet, there is no need to behave like this.
with one stupid remark you defeat all the good that you did before.
a decent person would apologize but I'm not holding my breath.
Stanislav and Andyr, just let it go. There's a lot of people in here at that level of understanding that behave more or less the same. Sometimes I think they should just have an advanced forum with a password to keep beginners out. Just consider the personality that it takes to get that kind of work done. I know. I work in IT. People in an advanced deep-dive can't usually see past their nose. They try to help and get more angry at themselves for getting mixed up with helping a noob. Although what he wrote sounds personal, somewhere in that big brain he thinks he's helping you.
Just keep asking your question. Someone will come around sooner or later.
Just keep asking your question. Someone will come around sooner or later.
Thank you, vdi-nenna. 🙂
I have indeed found others who were willing to advance me from my "newb" status - on 2 fronts. Firstly, to drive "LTSpice" to the level of knowledge to get out the table of 10 harmonic distortions and secondly, to organise a cascode. I have simulated setting up a cascode on each JFET and, strangely enough, this increases THD slightly - but this increase is on the 2nd HD only, all the others decrease. So I'm thinking the cascodes - as well as taking away the Miller capacitance - should make the phono stage sound more "tubey"! 😀
And btw - wrenchone did actually provide me with some help - for which I am grateful. I just had to go to other people to be able to make use of that help.
Regards,
Andy
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