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Old 21st January 2013, 05:03 PM   #1201
RCruz is offline RCruz  Switzerland
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Quote:
Originally Posted by analog_sa View Post
This reminds me that at some stage, much earlier in this thread i had some problems with the choice of Q90/Q99. There simply wasn't sufficient voltage across Q99 and i had to find a suitable Q90. Not sure if this was just a freak occurrence, as apparently my build is ultraprone to those, or some advice towards the selection of the fets can also be incorporated in the build guide.

Eventually it turned out that both channels' output buffers were also running at very different currents and for the sake of obtaining better symmetry had to replace R15 with a multiturn pot.
Cool request.

Inittialy I had issues with the output buffer also.... solved them by replacing the fets but did not understand the reason.
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Old 21st January 2013, 06:13 PM   #1202
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The top transistor in the Fet cascode has a certain voltage between gate and source, the so called Ugs or Vgs. The transistor down in the cascode, say the 2SK170BL runs at near zero Ugs. The difference in Vgs of the top transistor and the main transistor is the voltage that develops over Drain-Source of the down ( main Fet ) transistor. That voltage should not be too low because the down transistor is not very linear at very low voltages. Also ideally the Vgs diffenence should be the same in both channels. That requires to select the top transistors for Vgs, similar and as high as possible. Something between 3 and 5V is what we usually aim for.
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Old 21st January 2013, 06:23 PM   #1203
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You can interpolate the linearity of the 2SK170 from this curve that shows idle current at several voltages. You see that the first 2V are strongly bend. We would like to avoid that region. Over 3 V the curve is nearly straight. That means that the J-Fet is a very good constant current source in that region and that transfers into good linearity as a buffer.
This is of cause without cascoding and without the cascode current source we have in the Paradise. this two measures plus choosing the right condition for idle and Vgs give the Paradise buffer its exceptional linearity as long as the buffer works in class A.
This is the case when no more then the idle is drawn. For example we have 8mA idle and a 10kOhm load. The buffer can swing 80V in class A into that load. That is of cause not possible because we run the buffer on only plus-minus 18V.
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Last edited by Joachim Gerhard; 21st January 2013 at 06:28 PM.
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Old 21st January 2013, 08:16 PM   #1204
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Thank you Joachim.

i allready read something about minimal Vds here: lab page
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Old 21st January 2013, 08:45 PM   #1205
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I grew used to set Vds between 8 and 12v for the k170... more will only increase dissipation IMO.

When you say we must choose J 310 by Vgs.... How ?

I know there is linearity between Vp and Idss in the same batch of fets 2SK170BL Vp

So maybe we ca choose the J310 by Vp (matching them at higher than 5v for example)...
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Old 21st January 2013, 10:05 PM   #1206
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Well, in the La Boheme phono this is for the input stage working in transconductance mode . When you do the Vds voltage too high in an input of a phono stage the noise will go up because of rising gate current so it is a compromise between linearity and noise.
For the paradise buffer 3 to 5 V is fine.
For selecting Vgs in the J310 cascode Fet you can simply build the paradise buffer with Idss selected 2SK170. You can build a little jig from DIL8 sokets where you can insert the J310 and then simply measure in the real circuit.

Last edited by Joachim Gerhard; 21st January 2013 at 10:11 PM.
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Old 22nd January 2013, 06:50 AM   #1207
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Sorry guys for disturbe.

I reed every single word of this thread an do like all of you but now I ran into trouble.
I solder the PCBs with all the hints and tricks you gave me, matched the NPN and PNP in a little higher range (12%) and now this:
I managed to rise the powersupply with 24,7V put it in the powerinput and trimm the V+ and V- to +-18,00 V. After a Test of 8 hours I retrimm from 17,92 to 18,00V again. After that I solder the bridge and let the Caps settle in.
And here is the problem. after 8 hours settling I have the problem, that 2 Caps (V- 6800/6,3V) are wet on top and give little blisters. With other words they are gone.

What made I wrong? Hope for help
Thanks Christian
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Old 22nd January 2013, 07:17 AM   #1208
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Soldered them the other way round? Your cat peed on them?
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Old 22nd January 2013, 07:36 AM   #1209
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So breadboarding is the solution for me
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Old 22nd January 2013, 07:38 AM   #1210
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Quote:
Originally Posted by Libby123 View Post

And here is the problem. after 8 hours settling I have the problem, that 2 Caps (V- 6800/6,3V) are wet on top and give little blisters. With other words they are gone.

What made I wrong? Hope for help
Thanks Christian
Wrong polarity on the caps.

Replace those by new ones in the correct position.
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