Help Matching JFET's

[error401]

If you want to build a dedicated jig, the eBay chinese panel meters have the requested resolution, though I'm not sure how accurate or stable they are (probably not). For example: Universal Digital LED Volt\Current voltage panel meter - eBay (item 350436459354 end time Feb-08-11 14:24:33 PST)

[PMA]

http://web.telecom.cz/macura/testfet.pdf

[wrenchone]

If I bother to do a board, it will be with dedicated sockets for most common fet types/pinouts plus common small signal mosfets and no shilly-shallying around. There would be one control to dial in drain current and plug-ins for two monitoring DVMs. This would be similar to what I'm currently using to match fets, but more versatile.

[AndrewT]

Hi,
I use DVM to take all my measurements. I don't trust ammeters.
A 9V pp3 and a 100r resistor is great for batching jFETs.

use a croc clip or inline socket to short together the G & S.
Apply +ve battery to 100r. Connect 100r to Drain of NjFET
Apply -ve to G+S
A low Idss jFET that draws ~0.5mA will drop ~50mV across the resistor leaving Vds @~8.95V
Pq ~ 0.0005A * 8.95V ~ 4.5mW

Do the same for a medium Idss NjFET. If Idss ~5mA then the Vds ~8.5V and Pq ~45mW

Do the same for a high Idss NjFET. If Idss ~40mA then Vds ~9-[0.04*100] ~5V
A 40mA jFET will not pass 40mA @ 5Vds. Maybe 35mA. Let's assume that figure of current passing.
Vds~5.5V Pq~190mW That is going to fairly quickly raise Tj.

If you want to rough batch completely unknown jFETs then consider replacing the 100r with 200r and measure the Vdrop to read off Idss.

Thereafter, I believe pair matching using comparison of DUT to REF to be the only reliable method for us poorly resourced amateurs.

[DualTriode]

Hello All,
There is more here than I have a grip on. I have my copy of The Art of Electronics out with a highlighter and a stack of Posits.
It is interesting that we DIYers can more precisely control the performance of these parts by measuring and hand picking the parts we install. The first example is the source follower can be nailed down as a current source. For this application Idss looks to be the critical parameter. I will read more.
DT
All just for fun!

[wrenchone]

Not really - IDSS just tells you the maximum drain current for zero gate bias. This is not how you want to operate a source follower, as you won't be able to deliver any current to an outside load without going to positive gate bias. You instead want to operate with a negative gate bias (for N-channel device) at the desired drain current.

[AndrewT]

Originally Posted by wrenchone

Not really - IDSS just tells you the maximum drain current for zero gate bias. This is not how you want to operate a source follower, as you won't be able to deliver any current to an outside load without going to positive gate bias. You instead want to operate with a negative gate bias (for N-channel device) at the desired drain current.

The Pass B1 is an excellent example that breaks your rule.
Curl has been telling us for years that jFETs can be biased to 90% of Idss rather than the more usual range of 25% to 75% of Idss.
Curl also reminds us regularly that when Vgs goes slightly +ve, Id exceeds Idss, But, he does warn of excessive gate voltage and it's effect on the gate leakage current.

The Pass B1 and the Salas version referred to as DCB1 are both excellent source followers using jFETs biased at Idss.

[Ken Newton]

Originally Posted by AndrewT

The Pass B1 is an excellent example that breaks your rule.
Curl has been telling us for years that jFETs can be biased to 90% of Idss rather than the more usual range of 25% to 75% of Idss.
Curl also reminds us regularly that when Vgs goes slightly +ve, Id exceeds Idss, But, he does warn of excessive gate voltage and it's effect on the gate leakage current.

The Pass B1 and the Salas version referred to as DCB1 are both excellent source followers using jFETs biased at Idss.

That is an interesting point regarding the Pass B1. One which I've wondered about myself. A very small amount of positive gate bias could be applied to a JFET but then one begins to risk forward-biasing the gate-source junction. The high drain impedance provided by the (lower) current-source JFET will not by itself cause the (upper) follower JFET to forward bias. However, an insufficiently high driven load could could pull down the follower's source terminal so to flirt with creating a forward-biased condition in the JFET source follower.

I've wondered, why take such risks, though? Why not just add the single current-source JFET's source resistor and bias the whole stage a few milliamps below Idss? I can only assume that grey beards such as Nelson Pass and John Curl have found this to be more of a theoretical than practical concern.

[wrenchone]

Right, and why forward bias a follower, of all things?

Edit - another thought - I think I remember seeing fets running at or near Idss in apps like MC preamps. The signal amplitude there is small, and the driving impedance is low.

[DualTriode]

Originally Posted by Ken Newton

<snip>
Why not just add the single current-source JFET's source resistor and bias the whole stage a few milliamps below Idss? I can only assume that grey beards such as Nelson Pass and John Curl have found this to be more of a theoretical than practical concern.

Hello all,
Question at this Point!
Say we take a number of jfets with closely matched Idss and as described above each with closely matched resistors. The other jfet parameters are not matched or measured.
Will the current through the jfets be equal?
DT
All just for fun!