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Old 1st March 2010, 06:18 AM   #11
Mooly is offline Mooly  United Kingdom
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Originally Posted by fftulip View Post
Thanks, Mooly, I don't have that book but I do have Self's Power Amp book, and his new Small Signal book on order - can't wait for that one to arrive, hopefully it will have many good design ideas that will address these and other issues.
The "small signal book" may have exactly what you are after... there is a section on phono front ends that involves using an opamp to synthesise the load impedance required... all in the quest for lower noise.

Wait 'till you get the book
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Old 4th March 2010, 05:35 AM   #12
fftulip is offline fftulip  United States
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I hope to explain some of the causes and solutions for distortion due to impedance non-linearity. Keep in mind that I am not an analog or IC design expert. I'm just posting what I've learned from textbooks, articles, and internet forums. First, some information on JFETs. Below are pictures of the physical structure of how JFETs are fabricated. The first example is an N channel discrete JFET. Note how the N channel is sandwiched between the two P gate layers. You can see from this diagram how there can be significant capacitances between the gate and the source and drain.
Nfet.GIF
Now a P-channel JFET fabricated on a bipolar IC process with a P substrate (P channel JFETs are more common than N channel in op amps probably because they are more compatible with the bipolar process). Note that in addition to the previously mentioned capacitances, there can also be a significant capacitance between the gate and the substrate for an IC. Normally the substrate in an IC is connected to the negative supply voltage.
Pfetic.GIF
Now here is a diagram of a simplified small signal model for a JFET which includes these capacitances:
jfetmod.GIF
Cgss: gate to substrate capacitance
Cgs: gate to source capacitance
Cgd: gate to drain capacitance

The bad things about these capacitances is one, they can be large (especially with low noise JFETs), affecting frequency response, and two, the capacitance varies significantly with voltage, causing distortion (bipolar transistor capacitances don't very as much, but it can still be a problem). You can see the effect of voltage on the JFET capacitances on these graphs taken from the 2SK170 data sheet:
2sk170cap.GIF
Note that most data sheets show the capacitances as
Ciss: common source input capacitance
Crss: common source reverse transfer capacitance
because that is what they measure from the device terminals. Here are the equations to translate between the two sets of capacitances:
Crss = Cgd
Ciss = Cgd + Cgs
The gate to substrate capacitance in ICs is rarely if ever published, but seems to the predominant one at least for the usual bipolar junction insulated process (which typically has the P substrate shown above). Some op amps use a dielectrically isolated process which isolates devices from each other, and I'm guessing may reduce the gate to substrate capacitance. The Analog Devices App Note 232 applies to the process having the gate to substrate capacitance, and I don't know if it will apply to op amps using other processes.

Now, to reduce the non-linear effects of the capacitances, there are some things you can do:

1. Use devices that have low capacitances to begin with (unfortunately, this usually means more noise).
2. Operate with as low a source impedance as you can (this pushes the distortion effects to frequencies hopefully above the band of interest, if R*C is low enough), and try to balance the input impedances.
3. Operate at as high a voltage as you can to reduce the capacitances (note that in Groner's op amp distortion tests the input impedance linearity distortion usually goes down with higher supply voltages).
4. Try to operate at a constant voltage - this is where bootstrapping comes in.

Here is an explanation of what the bootstrap circuit in AN-232 does. If you go through the equations, you find that the bootstrap/substrate voltage is tracking the input voltage so that Vin-V(substrate) is kept at a constant voltage. This maintains a constant voltage across the input to substrate capacitor to minimize its non-linear effects. Note this trick does not maintain a constant voltage for the other JFET capacitances (Cgs, Cgd), but in the AD744 at least, their effects seem to be much less than the substrate capacitance.
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Old 4th March 2010, 06:34 AM   #13
jcx is offline jcx  United States
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ps bootstrapping or a bootstrapped cascode should reduce/eliminate common mode deltaV

differential mode deltaV is reduced by high loop gain

Dimitri's positive gain circuit with input common mode bootstrapping should hugely reduce impedance modulation and distortion as shown in his plots - although he boostraps a bjt input op amp and it may be the common mode nonlinearity term reduction that is being seen in the plots

if you want to use op amps then the real low noise option is the AD743/745

if you can accept some lf s/n loss then the AD8655 is cheap but would really need an output stage with gain in the loop to achieve acceptable headroom


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Originally Posted by jcx View Post
tried some digitizing sw - "plot digitizer" on sourceforge

I suppose the main lesson of AI is how hard it is to make a computer do things that are obvious and trivial for humans but it seems like these programs could be a little more automated - lots of hand trimming of the points was required

mathcad for display:

jfet solid lines, low noise cmos dashed

Input Voltage Noise vs Frequency from manufacturer's data sheets

Click the image to open in full size.

no warranty of correctness expressed or implied but it still looks like the ad743 is the one to beat - thank Scott Wurcer
for a really low noise discrete SE input the audioXpress circuit could be modified with bootstrapping of the jfet input drain resistor supply and op amp ps

but these aren't textbook circuits
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Old 14th March 2010, 07:12 AM   #14
fftulip is offline fftulip  United States
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Here are some examples of bootstrapping a cascoded JFET input circuit to reduce impedance linearity distortion. First, the input circuit of the OPA627 illustrates the idea. This opamp shows well controlled impedance linearity distortion according to Sam Groner's tests.
opa627.GIF
Q3-Q6 provide the cascode for the JFETs Q1, Q2 (I believe that Q5,Q6 act as current repeaters to send the I1 current to Q3,Q4). One of the main reasons for using a cascode is to reduce the effective capacitance. Without cascoding, a common source circuit's Crss/Cgss (see JFET model in previous post) is in effect multiplied by the JFET gain, this can result in hundreds of pF! The cascode load for the JFET pretty much eliminates this effect ("Miller effect"). B1, in conjuction with Q7,Q8, and current sink I2 provide the bootstrapped bias voltage for the cascode. You will note that the bias voltage is referenced to the JFET source instead of to ground, so it is in effect bootstrapped to the input voltage to provide a near constant voltage across the JFET.

Here is a cascoded circuit without bootstrapping (reference voltage to ground) with spice simulation of the JFET Vds variation. This particular circuit uses resistor loads instead of a current mirror like in the OPA627 in order to match a later published circuit that I will compare with. The simulation was done with generic 2N3904 and 2N5485 transistors instead of better quality parts because that's what was available in my simulator library.
nobcir.GIF
noboot.GIF
You will note that without bootstrapping, the voltage across the JFET follows the input voltage variations, so there could be significant JFET capacitance/voltage variation and distortion.

Now a cascoded circuit with a bootstrapped reference voltage, similar in concept to the OPA627 circuit, and the simulated voltage variation.
zenbcir.GIF
zenboot.GIF
Note the scale of the voltage variations, it is actually much less than the non-bootstrapped circuit, and on the order of a few millivolts. Also note that I was forced to run a zener reference (D1) at less than an ideal current because of simulator library limitations, so performance could be better than this if you used a micropower voltage reference like a LMV431 for example. Another possibility is a reversed biased transistor which often works well as a micropower zener. You want to use a micropower reference so you don't affect the bias current for the JFETs so much.

Another bootstrapped circuit using a JFET bias as published by Analog Devices in their "Op Amp Applications" manual (chapter 6), with simulation results (I used a 2N5432, which has a Vgs pinchoff of around -5 volts for the JFET bias).
jfetbcir.GIF
jfetboot.GIF
This appears to work quite well to limit the voltage variation for such a simple circuit. The issue with this method is that you need to select the JFET for its Vgs (look for a large Vgs off or pinchoff value) and you may be limited to a bias voltage of around 4 or 5 volts as there aren't many JFETs with larger Vgs values. In theory, you may be able to stack two JFETs to get a larger bias voltage, and it seems to work in a simulation I ran.

Now, slightly off topic as it isn't a phono preamp circuit, but here's an interesting example of a cascoded circuit (non-bootstrapped as far as I can tell, but the schematic is too blurry to say for sure) from a Hafler power amp. It is more sophisticated than usual for a power amp input. Note that it actually has bias voltages for the optional 2SK389/2SJ109 dual transistor subtrates ("S/S"). The subtrate bias voltages seem to be set at half the cascode voltage, I wonder how they determined that?
Hafler.GIF
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Old 6th December 2010, 03:12 AM   #15
jimtone is offline jimtone  United States
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Is the noise you guys are speaking of coming from the cartridge when you hold your hand close to it?? This is the trouble I'm having with my Realistic Lab 440 with a Sure cartridge. I've check to be sure the ground is connected securely and that the RCA cables are not touching, but when I get close to the cartridge, it makes a loud audio buzz thats almost like feedback. Does then cartridge need to be looked at or changed, or is there a chance it needs to be demagnetized?
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Old 7th December 2010, 04:01 PM   #16
kevinkr is offline kevinkr  United States
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Originally Posted by jimtone View Post
Is the noise you guys are speaking of coming from the cartridge when you hold your hand close to it?? This is the trouble I'm having with my Realistic Lab 440 with a Sure cartridge. I've check to be sure the ground is connected securely and that the RCA cables are not touching, but when I get close to the cartridge, it makes a loud audio buzz thats almost like feedback. Does then cartridge need to be looked at or changed, or is there a chance it needs to be demagnetized?
This is a very, very off topic post.. This thread has nothing at all to do with your issue. Does it otherwise work normally or does it hum a lot when playing? You shouldn't have any discernible increase in noise when your hands are in proximity of the cartridge - it sounds to me like the shield on your cartridge if present is not grounded or that the arm tube itself is no longer properly grounded. (Look for broken or corroded internal ground wiring connections.) Does your table have a ground wire and is it connected? MM cartridges like your Shure should never be demagnetized and IMHO this is of very limited value on most MC types as well.

Any Mod want to move this and the original question (Post #15) to a new thread?
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Last edited by kevinkr; 7th December 2010 at 04:03 PM.
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Old 8th December 2010, 05:47 AM   #17
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I have my doubts about the MM models after trying to measure the inductance of a cartridge on a lab bridge. The inductance seemed to be very frequency dependent, so I suspect iron losses were significant
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Old 8th December 2010, 05:51 AM   #18
jcx is offline jcx  United States
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ouch - you would need to keep measurement test signal levels to mV (< 10 mV?) to avoid saturating the iron for a "linear" measurement
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Old 8th December 2010, 07:37 AM   #19
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If the negative feedback is applied to the input stage as in the simple single opamp circuits, the effective input device gain and therefore Miller effect capacitance is going to vary with signal and when the device is struggling to track click transients.
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