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Old 5th November 2011, 01:01 AM   #3061
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Default transistors

I was thinking 2SA970 and 2SC2240 or BC550 and BC560.

And batteries

Can't wait!


atb,


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Old 5th November 2011, 01:05 AM   #3062
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That will work too.
Good luck.
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Old 5th November 2011, 01:08 AM   #3063
MiiB is offline MiiB  Denmark
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I look good, but can't see particular well...;-)
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Old 5th November 2011, 01:09 AM   #3064
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You should work as an actor (:
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Old 5th November 2011, 01:20 AM   #3065
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Default J-FET

Joachim,

What's the best IDSS for this circuit?

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Old 5th November 2011, 06:19 AM   #3066
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I would use BL grade ( Idss ca. 8mA ). My circuit degenerates that to 6mA. That is about optimum for least distortion. In a line stage there is no need for sub nV noise so we can afford some degeneration.
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Old 5th November 2011, 06:21 AM   #3067
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There is a very symmetric N and P channel pair from NEC that EUVL found that should also work well in my circuit. I just forgot the names.
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Old 5th November 2011, 07:39 AM   #3068
EUVL is offline EUVL  Europe
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You mean 2SK163 / 2SJ44 ?
It is even more impossible to get than the Toshiba's.
I ordered a few pairs as NOS fron Japan and had to pay a premium for those.


Patrick
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Old 5th November 2011, 02:19 PM   #3069
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That was what i am afraid of. When i look at the NEC-Tokin website they do not make transistors any more.
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Old 5th November 2011, 02:35 PM   #3070
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What can work is 2SJ103BL and 2SK246BL. If we degenerate them to 3mA we need a 900
Ohm trimmer and the drain resistors should be 2.5kOhm. That way we lower the gain of the input stage compared to the 2SJ74, 2SK170 combination. That could help linearity. What i do not like is the wide spread of Ugs with this Fets. The 2SJ103 needs 2.2V and the 2SK246
needs only 0.5V to degenerate to 3mA. So a conflict can arise between the output offset trim and the zero trim in distortion. Maybe i am wrong here because when both Fets drop 3mA over the drain resistors output offset should be fine even when the trimmer is a lot off from the mid position.
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