We want to maintain spec if possible. What you say is correct about voltage. Problem is we got to sort out Buzz with what he put in there now.
Let me see if I can make some. What about Lowering Rs on seond stage as way of bringing up drain voltage, taking it from 43 to 33. THis shouldnt affect RIAA, correct? I guess it would lower gain for second stage. It seems that 8mA onthe money is what is needed for Idss. I can get some from Spencer and reset in new build. Will allow me to correct error and redo some things on the board.
No, the opposite will happen. How much drain to gnd on second stage and how much Tp2 you can obtain with say 39V B+ after trying the Tp2 trimmer all over?
. Will do. Going to listen tonight. Report back.
If they are exactly matched then no one will current hog if with a common Rs. Since you double the current flow you need half the value to maintain the same local feedback (degeneration). Other than when using expensive boutique resistors and need economize there is no advantage VS one Rs per JFet which leaves slack for not that matched semis also. Rd? You mean the Jfets current sourcing resistor? That one derives from the total current drawn by the Jfets plus what you need flow through the common base cascoding BJT to have a range for TP1/TP2 centering. In conjunction with B+. That is why we use a trimmer locally to vary B+ for that CCS resistor. Its a balancing act. You solve against bias currents and B+.
Couldnt get it finished in time. Too many other activities took away the afternoon. Will resume tomorrow. It will give me the chance to get the other sslv up and running. Thanks for the help. I now understand the current hogging issue. Stepping away and thinking did me some good. Already got new boards drawn and correct jfets coming, as i do not have enough low idss fets to do one right. It willbe SMD again, with this one using Susumu. Should be good comparison of smd choices. I am going to bed. Long day. Thanks again.
So, using 3,9 for Rs, you use the jfets almost at Idss.
In my case Vgs = 29mV so I have 0.0074 Id on each fet
Double current (0.0149) flows on R13 (1k5) droping 22V
For R4 (2k2) we need 4Vdrop so current is 0.0018 that drops 3V on R13(1k5)
Total drop on R13 is 22+3=25v, so we need Vdd over R13 to be 33v so we have 8v on the bjt emitter.
35Vin-33=2V that must be droped on the trimmer... (0.0149+.0018)=0.0167 over the trimmer so it must be around 120r.
Easy to do on paper.. let´s see if I can compute it.....
In my case Vgs = 29mV so I have 0.0074 Id on each fet
Double current (0.0149) flows on R13 (1k5) droping 22V
For R4 (2k2) we need 4Vdrop so current is 0.0018 that drops 3V on R13(1k5)
Total drop on R13 is 22+3=25v, so we need Vdd over R13 to be 33v so we have 8v on the bjt emitter.
35Vin-33=2V that must be droped on the trimmer... (0.0149+.0018)=0.0167 over the trimmer so it must be around 120r.
Easy to do on paper.. let´s see if I can compute it.....
Almost done.
Salas, would you please post 1st stage gain in the case using double k170 in the input ?