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Old 8th April 2013, 09:35 AM   #9621
andyr is offline andyr  Australia
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I would be interested to hear from others what they think is the best current to have running through the JFETs.

I was told by an amp designer who has worked with JFETs, that 2/3rds IDSS delivers the best sound.

What do you understand?


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Old 8th April 2013, 09:40 AM   #9622
RCruz is offline RCruz  Switzerland
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In this case we are using the fet as a ccs, not an amplifier.... so I believe we do not run into any nonlinearities.... the issue might be that we can have lower noise at higher Id, but if I choose a lower value for vref resistor, I will loose Zo in the shunt so it is a compromise.
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Old 8th April 2013, 09:50 AM   #9623
andyr is offline andyr  Australia
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Quote:
Originally Posted by RCruz View Post
In this case we are using the fet as a ccs, not an amplifier.... so I believe we do not run into any nonlinearities.... the issue might be that we can have lower noise at higher Id, but if I choose a lower value for vref resistor, I will loose Zo in the shunt so it is a compromise.
Sure - sorry, I was thinking about the JFETs used for the 1st & 2nd gain stages ("sitting underneath" the CCSes).

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Old 8th April 2013, 10:46 AM   #9624
RCruz is offline RCruz  Switzerland
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In the simplistic, salas determines Id for best THD

Anyway we are using average 0.25Vp for Vgsq in second stage.

On the folded first stage we run the fets almost at Idss with great linearity.
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Old 8th April 2013, 11:08 AM   #9625
andyr is offline andyr  Australia
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Quote:
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On the folded first stage we run the fets almost at Idss with great linearity.
Aah, OK ... so higher than 2/3rds Idss is OK.

But how do you know there is "great linearity"?

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In the simplistic, Salas determines Id for best THD
Are you saying THD varies with different Id?

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Old 8th April 2013, 11:25 AM   #9626
RCruz is offline RCruz  Switzerland
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Quote:
Originally Posted by andyr View Post
Aah, OK ... so higher than 2/3rds Idss is OK.

But how do you know there is "great linearity"?
Look at the k170 charts, near Idss the curves are more linear
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Old 8th April 2013, 12:01 PM   #9627
AndrewT is offline AndrewT  Scotland
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Most jFET amplifier designers adopt Ic from 70% to 100% of Idss.
A very few builders, as different from designers, adopt a much lower Ic, some I have seen going as low as 10% of Idss.
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Old 8th April 2013, 12:34 PM   #9628
massimo is offline massimo  Italy
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I am using 30kr for vref so I need around 1mA to get 35Vout.

I chose a K117GR with 3.6mA Idss... the trimmer on the gate reduces this value to the correct Id.
Thank you Ricardo. Thus K117's Idss the lower the better, right?

I missed the point: why did you lower R11 from 47k to 30k? If I'm not wrong you double up the value of C1 too.

P.S. trimmer on the source, not gate I guess

Last edited by massimo; 8th April 2013 at 12:36 PM.
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Old 8th April 2013, 12:39 PM   #9629
andyr is offline andyr  Australia
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Thanks, RC & AT.


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Old 8th April 2013, 12:55 PM   #9630
Salas is offline Salas  Greece
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The folded runs at around 80% in first stage.
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