Simplistic NJFET RIAA

diyAudio Chief Moderator
Joined 2002
Paid Member
I think I would be interested in the same for my build. Cartridge is an AT ML440MLa. The K369 Idss I'd have to look at but think they are in the 11-12mA range. Intended loading will be ~33K. The cartridge is spec'd at 4mV output. Calculation results in ~48dB (log(1/.004)*20).
And most appreciate all of your work on this, and recently the discussion of measuring/selecting the LEDs using Q7.

Can't wait to listen to this; Thorens TD320 has been in storage far too long :)

This is a -10dbV home Hi-Fi standard output phono. In other words not to produce lower than 300mV RMS with the weaker cartridges in each category. That would be 3mV for MM. So with a 4mV output cartridge use the FSP's standard 40dB MM gain configuration. That should give 400mV with 5cm/sec reference groove velocity. Records can hit peaks well over that "zero" reference level and they would push the phono for THD and hiss if its configured too sensitive.

Usually turning the volume knob a couple of positions higher than with digital sources is enough. When more system gain is really needed, like when the loudspeakers are disappointingly quiet even when its past three o'clock on the knob from a vinyl source, add extra gain in the line level preamp's circuit.

Wishing you happy listening soon with the Thorens the AT and the FSP. They will be making a nice vinyl source bringing back memories. Let us know how it goes.

Tangerine Dream - Something To Remember Me By (1987 Three O' Clock High Soundtrack)
 
So here is a rather concise explanation of the FSP schematic in a single post. I hope it will be helpful to more members. We will not go into the whys of its topological and parts choices philosophy here. Just to the mechanics. Its a two gain stages plus buffer architecture discrete preamp. Lets see the stages one by one.

A. Input stage

The phono cartridge's signal goes through a switched loading choice system and its applied to the gates of Q1 & Q2 minimal noise type JFETS. Cooperating with Q3 BJT the stage's gain engine is formed. Q1 & Q2 are a common source amplifier while Q3 is a common base one that sits on their drains in series. The common base part shields the JFETS transcondactance from the load resistor R4. The technique is called "cascode" and its goal is not to let their gate to drain parasitic capacitance magnify more than a couple of times while the signal is still amplified to high gain by this JFET+BJT combination system. Else the total input referred capacitance would have escalated at same amplification rate as the signal's. Such capacitance boost is called Miller. We don't want it here. It brings various negative effects regarding proper cart loading, electrical resonance, bandwidth limiting. Especially for MM cartridges.

This cascode is also a kind that goes around to the ground point for reference than going up to the rail. Q3 is PNP while R4 loads it and folds over to GND. That is why its called a folded cascode. The much more common type that refers to the rail is called telescopic. It must still draw current from a power source nonetheless so R13 provides it as passive CCS. DC current flows through Q1 Q2 and R2 R3 to ground. They ask for a certain amount as a system dependent on IDSS and degeneration. What is surplus goes through Q3 to R4. It creates a collector output DC voltage we want to keep at about half the value where Q3's base sits. Q7 is a JFET CCS that sends current to D1-D4 LEDS creating with their VF a steady DC voltage point for Q3's base. C8 filters for noise. Across R4 the output signal develops by the action of Q3. R12 and R15 make proper DC drops in the circuit. C6 & C7 form local filters with those.

Rail voltage value, R12//VR1, R13, Q1 Q2 IDSS, R2 R3, all form a balance system which is both pre-calculated and trimmer adjustable to set the two bias currents of the cascode combo in correct analogy. To monitor and adjust the resulting DC voltage difference between Q3's base and collector, test points are marked on the PCB (TP1 TP2). The PSU's variable output voltage setting adjusts the system while VR1 lends a finer touch if needed.

B. RIAA and the second stage

There is no negative feedback loop between stages in this preamp so it can't nest some interstage active filter. A passive RIAA filter network of no "lost constant" addition is located between stages one and two. R14 R5 C1 C2 form its base impedance and LF/HF filter curve branches. R6 is corrective to R5's standard value, makes it more precise, or a special value R5 can be used skipping R6. There is also a C2Y pF range capacitor place on the PCB to complement C2's value against tolerances or towards preference. They are the important HF branch. Both the input stage's source impedance and the second stage's Miller effect have been included in the total filter's tuning. C3 AC couples the equalized signal to stage two. R7 refers Q4 JFET's gate to ground. R10 is its drain load and R8 is its source degeneration providing some judicial amount of local feedback to better THD. This single high transconductance JFET common source stage is potent enough for further amplifying to the final output voltage swing goal. Aiming at 300-400mV AC RMS with most cartridges. As recommended for LMC/MC/HMC/MM nominal output ranges and the circuit's proper sensitivity configuration options in the build manual. The DC level created between R10 and Q4's drain is also the voltage reference point for the output buffer circuit.

C. Output buffer

Q6 copies the signal as seen at its gate while performing current gain only. It is a source follower. Through C4 AC coupling the buffered signal finally outputs. There are no degeneration or damping resistors. Thus the output impedance is no more than the intrinsic RDS. Usually 30-50 Ohm for this JFET type. Q5 is configured as an IDSS current source and determines the current bias of Q6. R9 provides a local discharge path to C4 not to suddenly do it when connecting gear. R11 and C5 form an RC filter for proper voltage drop to center the buffer in regard to Q6's gate voltage bias. It also performs some local noise cleaning.

I hope it was a simple enough description to follow. I linked it in post#1 too. For the FSP's integrated PSU please refer to the BIB SSLV1.1 shunt regulator as they are highly related. The SSLV1.1 build thread


Where do I find the complete schematic, with parts values?
 
Salas,

Probably a tricky question, but it's not intended to create any cnnfusion. It was probably made somewhere in the 1700 pages of this thread.

This thread started in 2008, where most fets were still available from trusted vendors. Of course I'm talking about the 2SK170 and 2SK369. Now you have to pay very high prices for them if you want to stick to the IDSS requirements, as getting twenty or more of each to get the ones you need sounds difficult and expensive, besides the unreliability of fake parts.

Are there any other FETs you would recommend for those parts? Preferably those stocked by Mouser, Digi-key, Future=Electronics or even Trendsetter, in case of using duals for i.e. Q1-Q2.

Has anyone walked this path for this project?
 
Member
Joined 2006
Paid Member
LSK170s for 2SK170s that you may find around and Tea-Bag still has matched original 2SK369s for its input stage I think. You can just put a textbook anti-RIAA filter between the voltage source and the circuit's input in LTspice.

Salas also guided me on how to alter some resistors in case Q4,Q5 are not in specifications. I think the only solid rule is Q6>Q5. The IDSS ranges for those are indeed hard to procure from original specifications.
 
You can just put a textbook anti-RIAA filter between the voltage source and the circuit's input in LTspice.

There are quite a lot anti-RIAAs in the web!

Would this by Rod Elliott be fine?

Do you suggest any other?
 

Attachments

  • Elliott anti-RIAA.jpg
    Elliott anti-RIAA.jpg
    39.6 KB · Views: 410
Last edited:
diyAudio Chief Moderator
Joined 2002
Paid Member
Salas also guided me on how to alter some resistors in case Q4,Q5 are not in specifications. I think the only solid rule is Q6>Q5. The IDSS ranges for those are indeed hard to procure from original specifications.

Best is Q6=Q5 but when they are somewhat unequal (as usual bcs stellar matches are nowadays hard to find and the better ones are to be saved for Q4s between channels) then always place Q6>Q5
 
Hi Nick
I'm having my phono full assembled in a carton box(for time being, so no photos for now) and plays very nice
Still waiting for break in period of my new Denon 301 (and the phono of course)
I did try a new Raw PP filter , i add a 7H 150mA choke and another 4700 on the end of the choke, so i have a CLC filter. The problem is that I calculate the transformer for 230V and i'm having 225 max most of time, so my Raw DC now is maximum at 44.3V
With CLC i see more "clear" sound , pin point instruments, more depth in image. not sure if i have less dynamics. Is the 44.3V Raw DC enough for the CCs and shunt Reg? I'm almost on my way to order new transformers with 225V AC input rather than 230V.

Thanks in advance
Thanos
 
Last edited:
diyAudio Chief Moderator
Joined 2002
Paid Member
Thanos, no practical worries when Raw DC is >5V than RegOut on the mains daily average.

At 10V difference its just a somewhat faster CCS because any Mosfet shows less internal capacitance with higher VDS across it. That helps to bit more refined highs. When reaching 25V across the IRF9610 there is no parasitic capacitance lessening anymore. But its a fast type so its not making a big difference. We can't do more than 15V here anyway because other elements in the reg will not take more than 50V Raw DC safely. Because its a small current demanded here we have the heat exchange luxury to do more than 5V VDS as long as the heatsink remains logically hot. That's all.
 
Thanks Nick
About the highs, and the C2Y treble trim
I feel that I have somewhat recessed highs (hi hats, etc) with turntable compared to CD playback but I do not have an exact recording to compare, it's mostly a sensation
So far I have C2 at 15nF (not accurate measurement) and a 150pF WIMA from the kit
So in theory I have 15.15nF total C2 and C2Y
do you think that i need to reduce C2Y or take it out to see the difference?
 
diyAudio Chief Moderator
Joined 2002
Paid Member
Take it down to 15.1nF and 15.05nF step by step i.e. C2Y 100pF then 47pF just stop where satisfied. Those 1% Vishay C2 15nF are usually on the plus side value
For a tonal orientation coarse test you can just remove C2Y and listen to the effect on the treble trend of course. Until you will have finer step C2Ys in your hands
Trust yours ears for what your system needs especially when not having a flat to 0.5dB lab generator, an accurate anti-Riaa test box, and a very good LCR meter
 
Still high :(


Its high AC. But no worries, because there is provision. Where the raw pcb has the RD/Link marked positions put 47-50 Ohm 5W resistors. That should drop enough Volts.

Test the raw DC outputs across 560 Ohm 10W dummy load resistors before connecting it to the main circuit. Around 45 VDC when loaded will be fine. In case it proves too low or too high DC we will readjust the RD/Link dropper's value.

Normal quality cement resistors (like those white bricks in passive speaker crossovers) will do the job alright.
 

Attachments

  • D6E92D2D-F01D-477D-93DB-2F6F5D4C4CAD.jpeg
    D6E92D2D-F01D-477D-93DB-2F6F5D4C4CAD.jpeg
    577.9 KB · Views: 381