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Old 17th August 2010, 12:12 AM   #4441
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20.16V guess that is "about" ;-)
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Old 17th August 2010, 12:18 AM   #4442
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Hmm R6 (2nd stage's Rs) is 33R... That Jfet seems isn't 8.8mA IDSS, looks like less. When the buffer's Jfets draw as IDSS stated. Is your R10 6k8? Can you add 1.2k in series with R10? That will give even more gain and it will centre the buffer. Look for 10V on second stage's drain.
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Old 17th August 2010, 12:37 AM   #4443
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how about I put the right jfet pair in?
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Old 17th August 2010, 12:41 AM   #4444
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Now that they are put there, and there is good channel matching I would prefer more gain with 8k R load total. Now you got more 2SKs from that shop down the road?
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Old 17th August 2010, 12:55 AM   #4445
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I was too quick. Before I saw your reasoning I changed them. I did a quick check on the channels and they still match. See Attached.

The buffer are now sitting at 11.6 on right and 11.4 on Left

Sorry about that, but from my perspective and in hindsight, it it alot easier then redlining all of the schematics. I also would prefer not to have too much more gain. The thing allready blows the windows out.

If I did my math right, I need about 150R now

P.S. guess I should attache the graph
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File Type: jpg RIAA Channel match with proper buffer.jpg (150.0 KB, 148 views)
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Old 17th August 2010, 12:59 AM   #4446
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You will have a bit more, now that you put the properly strong. Check gain and THD with 0.3mV in. Lets see where we are before adding any R. There is Rs we can up a little along more load as well and win some THD.
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Old 17th August 2010, 01:04 AM   #4447
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Quote:
Originally Posted by SGregory View Post

P.S. guess I should attache the graph
Your RIAA curve looks better than your first shown before many posts. Could not reach the -40dB first because your FFT was not doing enough HF low floor, now you use your laptop battery only its almost there. What is that supersonic V?
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Old 17th August 2010, 01:20 AM   #4448
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Glitch in correction file.

Here is the 1kHz FFT.
Gain is 57.9 dB using .3mV input which is also 0dB on plot
THD is down at 0.021%Right and 0.015% Left

Noise floor is up slightly, but both the internal and external box is open
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File Type: jpg 1kHz FFT proper buffer.jpg (194.6 KB, 146 views)
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Old 17th August 2010, 01:26 AM   #4449
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Its OK. I had calculated G=58dB on your CCT with 8.8mA IDSS on 2nd stage. Its printed on it. Now THD is on target too. I started the questions after I saw odd stuff in you 3 color curve one. So we found the wayward guys. Where are the originally intended ones? In the PSUs I guess.

P.S. Can we directly compare the above graph with a new one, same standards, but all lids closed?
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Old 17th August 2010, 01:32 AM   #4450
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Nope. The proper ones were sitting on the sheet. I even had notes on them. Go figure, it was late that night. From what I can tell, I put in 6.8 or something. I am relatively confident that whatever I put in was at least matched per channel......
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