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Old 3rd December 2008, 05:08 PM   #421
AndrewT is offline AndrewT  Scotland
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and I cannot recall anywhere that recommends running the Id=150% of Idss.
The B1 in optimum state certainly doesn't and cannot be used as a valid reference for your design choice.
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Old 3rd December 2008, 05:10 PM   #422
AndrewT is offline AndrewT  Scotland
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Quote:
Originally posted by salas


What do you see in my sim pic post? 11.45mA centre and AC hovers around. So you answered it. Drain is virtually AC grounded, remember. So we avoid an extra capacitor between 2nd stage and buffer, or a symmetric supply. Tricky Salas, shame on you.
tricky? no.
The quiescent state is 11.45mA and this is ~150% of Idss if you chose 7.5mA Idss as your device.
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Old 3rd December 2008, 05:18 PM   #423
Salas is offline Salas  Greece
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Quote:
Originally posted by AndrewT
and I cannot recall anywhere that recommends running the Id=150% of Idss.
The B1 in optimum state certainly doesn't and cannot be used as a valid reference for your design choice.
It can be as for the chosen voltage across, for the chosen Idss device and the way it distorts, not for the current quiescent condition. I refer only to the voltage across. Of course I use more current. Posted simulator pics that clearly show. If you feel like relaxing it I also posted values to Jonners for 6.6mA. But it works, and works nicely. 2 examples made.

Quote:
Originally posted by AndrewT
tricky? no.
The quiescent state is 11.45mA and this is ~150% of Idss if you chose 7.5mA Idss as your device.
Semantics. Say not tricky, say non conservative.
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Old 3rd December 2008, 05:24 PM   #424
AndrewT is offline AndrewT  Scotland
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Would anyone care to comment on whether one can get good performance from a jFET follower if the design Id~150% of Idss?
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Old 3rd December 2008, 05:46 PM   #425
Salas is offline Salas  Greece
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I would but its not nice, since I did it. I have B1 too to compare. Maybe Lee can, since he uses an example of mine. Of course the buffer choice is open, someone can strap a B1 style buffer or white follower Njfet style buffer a la Borberly. No reason to follow strictly my practices there.
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Old 3rd December 2008, 05:59 PM   #426
Salas is offline Salas  Greece
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Some more alternatives.
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Old 3rd December 2008, 06:39 PM   #427
jonners is offline jonners  United Kingdom
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How interesting! Seems like I started off a lively little discussion, guys!
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Old 3rd December 2008, 06:51 PM   #428
Salas is offline Salas  Greece
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For your follower choice, eh, follow your heart!
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Old 3rd December 2008, 08:35 PM   #429
Salas is offline Salas  Greece
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Default Neg Led PSU bro

So, some may explore other buffers, which may need symmetric supplies.
Also Nicoch has asked for a negative PSU some time ago. Someone from the B1 thread asked too.

Here I post the symmetric neg ones. Haven't made any, I have no use, they should work nicely as mirror images since the positive already works with no problems.

The first one is the negative of the one that uses 2SK for the LED CCS. Alas, the 2SJ74 is 25V limited, so we can't exceed Vin-VLeds>25V.
So its good if you have some 2SJ74s in your stash and you are using a capacitor less B1 buffer or something else using up to +/- 20-22V.
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Old 3rd December 2008, 08:50 PM   #430
Salas is offline Salas  Greece
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And the second one. This uses a Wilson current source for the LEDs. 60V ''ring of two'' transistors can be used higher. I simulated the symmetric of the page 16, post #399 Cygnus X1 example.

You know by now, scale the Zener, use 6-8 -Vin more than -Vreg, for your chosen voltage, which is Vz+Vbe or about, depending on Zener's tolerance to its nominal value. The LEDS must be measured for the string of 3 Vdrop. ICCS=(LEDSVdrop-3.4)/R1.
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