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low distortion 6 transistor preamp
low distortion 6 transistor preamp
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Old 14th August 2017, 01:47 PM   #31
audio_tony is offline audio_tony  United Kingdom
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Originally Posted by jpc2001 View Post

Edit: I agree with your images from post 27, this is where clipping starts with the 2.2k load. So, there's not much headroom between 3V (the max amplitude we might really use) and 4V (onset of clipping) and we might want more headroom than this. As you suggest, a current source would do it. We also have more headroom if you assume the power amp input impedance is more typical like 10K+.
Thanks - you were making me doubt myself for a moment.

Another thing I picked up on during messing around with the sim was instability - I thought I had seen oscillation, but I didn't look any further.

I'm not that familiar with LTSpice - but the FFT looks a bit odd with the twin peaks, and the bottom graph looks like bursts of oscillation (unless I'm misinterpreting the graphs!).
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Old 15th August 2017, 02:15 PM   #32
jpc2001 is offline jpc2001  United States
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I built this circuit. The final set of .asc and .asy files are in the attached zip, these match the circuit as-built.

"pre_new.asc" is a top-level shell to drive the simulator; other files correspond to hardware.

Everything at and below "pre_pcb.asc" is one PCB. I've split it into modules to avoid duplicating the left and right channels in schematic, to avoid duplicating the identical 2nd and 3rd gain stages, and to allow simulating each gain stage independently.

This PCB is a drop-in replacement for the tone control board in a Pioneer SA-9500 mk2. It works with the original tone pots and uses the factory values for baxandall networks.

The boundaries of the gain stages (microamp.asc and microamp2.asc) are a bit odd. Why not include the compensation caps within the gain stage? I did it this way to allow instantiating the gain stages in a little testbench (not shown here) to evaluate loop gain and stability.

I'm not posting the layout because it's not ideal. Some high-impedance traces are longer than they need to be. Also I did several mods after the board was built to reduce noise pickup and improve stability margins, so the final schematic no longer matches the .pcb file.

Components in the schematic whose names contain '_open_' are not present in the real circuit; these represent parasitic caps. Similarly, components whose names contain '_closed_' are simply wires in the real circuit; these represent parasitic inductances or "spice ammeters." I run a perl script to convert the LTspice netlist to a Gnu Pcb netlist (for drawing the rat's nest) and it discards these open/short components.
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Old 28th August 2017, 01:57 PM   #33
jpc2001 is offline jpc2001  United States
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An erratum in the fileset from post #32:

The output will swing positive several volts for several seconds at power on. This can reverse bias a power amp's input capacitor, if it's an electrolytic, and risks damage.

The fix is to replace the 33uF output caps (C17 and C49) and their 150k load resistors (R21 and R59) with 2.2uF film caps and 47k.

That reduces the voltage excursion to under 2V. I also modified a cap value in the voltage regulator that supplies VPOS so that it rises more slowly, and that gets the excursion down to about 1V which is probably just good enough for safety.
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