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Old 25th January 2016, 07:29 PM   #1
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Default 4-channel gain stage with power supply

A couple of years back I designed a 4-channel gain stage (line stage) board. Since that time I have revised the design, and I would like to put it out in the public domain for personal (non-commercial) use. The preliminary layout and schematic are attached.

The design includes onboard power supply. In the case that the user already has an appropriate high quality power supply the components in the PS section can be omitted and power supplied to the board via an onboard DC power connector. In the case that the PS section is used, power can be taken from the board from this same connector and used to power other equipment. Note that a dual secondary transformer (not center tapped) or two separate transformers can be used with this design. CRC filtering is used to reduce charging pulses. Regulation is via 317/337 devices with cap stabilized adjust pin.

There are four independent gain stages, in pairs, designed around dual op-amps (I show LME49720). The input of each gain stage passes through an RC (EMF) filter and the input ground is lifted via a 4.7R resistor (or similar low value). The lift is used because the inputs are located away from each other and a loop can be formed via the grounds when paths are separated. The resistance should reduce induced currents and, therefore, hum and noise pickup. The amplifier outputs have local HF decoupling and use 68R loading.

I've tried to use sane design and layout concepts. There are multiple star grounds. I am sure that I can still learn a thing or two or three.

Please feel free to comment on this design, point out weaknesses or areas for improvement, etc. I plan to post the production files here after it has had a chance to be vetted.
Attached Images
File Type: png PS_section.PNG (32.4 KB, 273 views)
File Type: png gain_section.PNG (28.4 KB, 268 views)
File Type: png 4ch_gain_stage_revC.PNG (117.9 KB, 267 views)
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Old 25th January 2016, 09:25 PM   #2
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Sounds like you're looking for next steps for improvement. I'd suggest greater familiarity with layout parasitics and noise injection mechanisms. Marce posts on this extensively. Tomchr's taming the LM3886 page and related layout posts in the chipamp forum may also be of interest.

On a functional level it may be interesting to look into difference amplifiers and consider lower cutoffs for greater RF/EMI (EMF means something a bit different) rejection. Shifting down a bit in frequency may also be of some interest in the RISO compensation, depending on the desired amount of tolerance for load capacitance.

Probably more current is being pulled from the regulators than is necessary here, though it's not a big deal. Nice job on including protection diodes. But check the polarity of D1 and D2.
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Old 25th January 2016, 10:17 PM   #3
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Originally Posted by twest820 View Post
Sounds like you're looking for next steps for improvement. I'd suggest greater familiarity with layout parasitics and noise injection mechanisms. Marce posts on this extensively. Tomchr's taming the LM3886 page and related layout posts in the chipamp forum may also be of interest.

On a functional level it may be interesting to look into difference amplifiers and consider lower cutoffs for greater RF/EMI (EMF means something a bit different) rejection. Shifting down a bit in frequency may also be of some interest in the RISO compensation, depending on the desired amount of tolerance for load capacitance.

Probably more current is being pulled from the regulators than is necessary here, though it's not a big deal. Nice job on including protection diodes. But check the polarity of D1 and D2.
Thanks for your comments. I was hoping for slightly more specific feedback... I could pour over tomchr's posts ad nauseum but nothing would dawn on me... I'm too green at layout to even know what I don't know, or where I could improve.

Can someone point out areas that could be improved with a little more detail and specificity?

Also, is the existing design OK for audio, or are there serious flaws?

Thanks.
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Old 25th January 2016, 10:23 PM   #4
rayma is offline rayma  United States
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Originally Posted by CharlieLaub View Post
Can someone point out areas that could be improved with a little more detail and specificity?
This is a 55MHz op amp, so a top layer ground plane is needed, preferably with smt local decoupling caps.
Use the SOIC device package for best results.
Also place C1-C4 as close to the inverting and output pins as possible, and use smt cog/npo types for these.

Last edited by rayma; 25th January 2016 at 10:33 PM.
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Old 25th January 2016, 10:24 PM   #5
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OKness depends, in general, upon precision targets. If you're good with probably, oh, -80dBish errors and a few dB of CMRR the approach here is fine.

For layout I'd suggest first understanding how copper geometry affects RLCG parameters and after that relating back to circuit performance.
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Old 25th January 2016, 11:13 PM   #6
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Originally Posted by rayma View Post
This is a 55MHz op amp, so a top layer ground plane is needed, preferably with smt local decoupling caps.
Use the SOIC device package for best results.
Also place C1-C4 as close to the inverting and output pins as possible, and use smt cog/npo types for these.
Unfortunately only hole components can be used on this project. Is there a better lower GBW op-amp for audio band and gain around 6dB - 12dB?

There are local decoupling C0G caps close to the power pins.

Can you explain why a ground plane is needed if the bandwidth is restricted by the feedback cap? This wouldn't attenuate HF above the audio band? I could move these closer to the device pins (next to them).
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Old 25th January 2016, 11:17 PM   #7
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Pours aren't necessarily required, though reducing layout inductance is seldom a bad idea. Tim Green's series on op amp stability will help with understanding how the 1/beta intercept moves with GBP and signal gain.

The TI/Burr-Brown OPA 16xx parts are good alternatives to the LME497xx series.
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Old 25th January 2016, 11:22 PM   #8
rayma is offline rayma  United States
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Originally Posted by CharlieLaub View Post
Can you explain why a ground plane is needed if the bandwidth is restricted by the feedback cap?
This wouldn't attenuate HF above the audio band? .
At 55MHz the device/component/pcb parasitics require careful layout.
Even a via can cause problems.
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Old 25th January 2016, 11:46 PM   #9
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Originally Posted by rayma View Post
At 55MHz the device/component/pcb parasitics require careful layout.
Even a via can cause problems.
I thought this was only the case if there were 55MHz signals running around the circuit. Is it a good idea to just assume that these will be picked up from ambient RF?
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Old 25th January 2016, 11:52 PM   #10
rayma is offline rayma  United States
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Originally Posted by CharlieLaub View Post
I thought this was only the case if there were 55MHz signals running around the circuit.
Is it a good idea to just assume that these will be picked up from ambient RF?
The op amp can make its own hf from the energy in random noise.
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