Idea for this buffer came from forum member who needed simple volume control for the input of Bonsai's nx power amplifier. PMI volunteered to design small pcb for a possible future GB.
Design criteria for this buffer are:
1. pcb will have onboard pot that will allow simple front plate one hole mounting. pcb will be small enough to fit any power amp chassis
2. Pot will be high quality ALPS Blue Velvet RK27. Pot shaft will be used to hold the pcb to front plate
3. pcb will have simple zener regulator + RC filtering onboard so that the whole circuit could use existing power amp supply/transformer. Additional holes could be provided on pcb for those who intend to use better offboard regulation
With the addition of rear toggle switch placed between two pairs of RCA connectors and using short unshielded wires, this buffer pcb could transform any power amp into integrated amp with two line inputs. With the addition of Lorlin 3way/4pole rotary switch and using shielded cables (with or without extension shaft) this buffer could transform any power amp into integrated amp with 3 line inputs.
If current consumption of the circuit is known, we could calculate voltage dropping resistor for any power amp supply...
Design criteria for this buffer are:
1. pcb will have onboard pot that will allow simple front plate one hole mounting. pcb will be small enough to fit any power amp chassis
2. Pot will be high quality ALPS Blue Velvet RK27. Pot shaft will be used to hold the pcb to front plate
3. pcb will have simple zener regulator + RC filtering onboard so that the whole circuit could use existing power amp supply/transformer. Additional holes could be provided on pcb for those who intend to use better offboard regulation
With the addition of rear toggle switch placed between two pairs of RCA connectors and using short unshielded wires, this buffer pcb could transform any power amp into integrated amp with two line inputs. With the addition of Lorlin 3way/4pole rotary switch and using shielded cables (with or without extension shaft) this buffer could transform any power amp into integrated amp with 3 line inputs.
If current consumption of the circuit is known, we could calculate voltage dropping resistor for any power amp supply...
Attachments
Thanks for starting this Ivanlukic. I propose to cascode the input JFET to improve PSRR. It will have to wait though until I am back from vac and can play with it in LTspice.
Mechanically speaking, this could also be mounted using a U bracket with lips at the rear of the amplifier to avoid running screened cable connections to the front panel and the possibility of noise. In this case, you would need to use a shaft extension coupler to couple the knob to the rear of the amplifier.
Load for this buffer will be 2k Ohms min, 10k nominal which should cover just about any eventuality.
Anyway, I'll do some work on it towards the end of next week.
Mechanically speaking, this could also be mounted using a U bracket with lips at the rear of the amplifier to avoid running screened cable connections to the front panel and the possibility of noise. In this case, you would need to use a shaft extension coupler to couple the knob to the rear of the amplifier.
Load for this buffer will be 2k Ohms min, 10k nominal which should cover just about any eventuality.
Anyway, I'll do some work on it towards the end of next week.
I hope not! PMI and I are old enough to avoid SMD. Original idea was to use J111 or similar, but Bonsai will suggest something later that is not too hard to find. You know, eyes are not as used to be....
Hi ivanlukic.
1. please decouple Zener diodes with 47...100 µF 63 V caps and use separate 100 Ohm resistors in the supply lines for each channel. Each channel will have its own 2 x 100 µF decoupling caps on the supply lines. You could also add pads so LM317/337 can be used. Or better, a nice dual (SMD !!!!) reg like the LT3032-12:
http://www.linear.com/product/LT3032
You will need to lower the input voltage to under 20 V so either preregs or 2 x 18 V 1 W Zeners should be used.
Unobtainable here but still:
http://www.irf.com/product-info/datasheets/hirel/om7500sm.pdf
I still use LM325, XR4195 and M5230 but those are very old and possibly hard to find. Especially the M5230 is a nice low noise chip.
2. Some RC input filtering would not hurt either. - 3dB point around 100 kHz.
3. An output GND reference resistor in each channel would make the PCB more versatile.
4. Additional pads for an optional input cap for those that have DC coupled sources with offset would be nice too.
1. please decouple Zener diodes with 47...100 µF 63 V caps and use separate 100 Ohm resistors in the supply lines for each channel. Each channel will have its own 2 x 100 µF decoupling caps on the supply lines. You could also add pads so LM317/337 can be used. Or better, a nice dual (SMD !!!!) reg like the LT3032-12:
http://www.linear.com/product/LT3032
You will need to lower the input voltage to under 20 V so either preregs or 2 x 18 V 1 W Zeners should be used.
Unobtainable here but still:
http://www.irf.com/product-info/datasheets/hirel/om7500sm.pdf
I still use LM325, XR4195 and M5230 but those are very old and possibly hard to find. Especially the M5230 is a nice low noise chip.
2. Some RC input filtering would not hurt either. - 3dB point around 100 kHz.
3. An output GND reference resistor in each channel would make the PCB more versatile.
4. Additional pads for an optional input cap for those that have DC coupled sources with offset would be nice too.
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Hi jean-paul,
I am not going to design pcb, it will be done by PMI. And the circuit design is Bonsai's, and not yet finished. I am just facilitator and promoter of this idea, hoping to help. We shall have to achieve some measure between complexity of the circuit, PSU and size of pcb. I think that your comments are more than welcome and does not require too much space on the pcb. This is collective effort, we want as much relevant comments as possible.
I am proposing
1. CCS for the JFET will be the two transistor type (flexible and easy)
2. Bootstrap the JFET for input capacitance mitigation - use BIP device to buff output and drive bootstrap cap and follower
3. Agree to add input filter - but then amplifier input filter must be modded or removed.
4. Agree that each channel should be separately filtered and decoupled
5. 3 term regs will add complexity . . . Do we really need that?
6. CCS and bootstrap will make PSRR VERY high plus decoupling on top of that
7. Small PCB with all components . . .
8. Important that the buffer can use any JFET with Idss above about 10 to 12 mA and not SMD. I am thinking J113 type devices - any recommendations gladly accepted
9. All trannies will be BC547/557 C types
10. Input DC blocking cap option - ok will add this. The volume pot will therefore be spec'd for 10k log or higher.
1. CCS for the JFET will be the two transistor type (flexible and easy)
2. Bootstrap the JFET for input capacitance mitigation - use BIP device to buff output and drive bootstrap cap and follower
3. Agree to add input filter - but then amplifier input filter must be modded or removed.
4. Agree that each channel should be separately filtered and decoupled
5. 3 term regs will add complexity . . . Do we really need that?
6. CCS and bootstrap will make PSRR VERY high plus decoupling on top of that
7. Small PCB with all components . . .
8. Important that the buffer can use any JFET with Idss above about 10 to 12 mA and not SMD. I am thinking J113 type devices - any recommendations gladly accepted
9. All trannies will be BC547/557 C types
10. Input DC blocking cap option - ok will add this. The volume pot will therefore be spec'd for 10k log or higher.
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Hi,
I´m not sure if a high PSRR is something required and that the added complexity will improve matters, especially sonic behaviour.
Cascoding the JFET with a second JFET -eg the very fine 4393/4391 combination- will only benefit with high load impedances >20k and high Ids.
With loading below 20k the single JFET could be better THD-wise.
Maximum voltage swing will be reduced by the cascode to ~4-5Vrms
Cascoding reduces power heat losses with the JFETs.
If the CCS is tuned to the Idss of the JFET one might even omit with the DC-blocking cap. I´d suggest to use a second identical JFET as CCS in that case though, because of thermal stability.
jauu
Calvin
I´m not sure if a high PSRR is something required and that the added complexity will improve matters, especially sonic behaviour.
Cascoding the JFET with a second JFET -eg the very fine 4393/4391 combination- will only benefit with high load impedances >20k and high Ids.
With loading below 20k the single JFET could be better THD-wise.
Maximum voltage swing will be reduced by the cascode to ~4-5Vrms
Cascoding reduces power heat losses with the JFETs.
If the CCS is tuned to the Idss of the JFET one might even omit with the DC-blocking cap. I´d suggest to use a second identical JFET as CCS in that case though, because of thermal stability.
jauu
Calvin
The original idea was to keep it as simple and practical as possible even if the lab performance will be less than ideal. I think that we should keep the basic concept of 1 j-fet + 2 bjt from the post #1 and refine PSU a little bit with separate filtration for each channel suggested by jean-paul. Also, input low pass filter will make it more versatile, plus input coupling cap, but output resisitor to ground is always provided by the input of power amp, although a place on the pcb for such resisitor will also make the whole pcb more versatile and does not require much space.
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Make it simple and good but not too simple and less good I think you will conclude that if you want to keep the device small with necessary bells and whistles SMD parts are unavoidable (I know, I hate them too but use them often).
BTW output GND reference resistor is for charging the output cap when no load is connected. You avoid large plops when connecting the device to power amps.
I think you will conclude that if you want to keep the device small with necessary bells and whistles SMD parts are unavoidable (I know, I hate them too but use them often).BTW output GND reference resistor is for charging the output cap when no load is connected. You avoid large plops when connecting the device to power amps.
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Hi,
the circuit in #1 is singleended class-A.
The maximum output current into the load is limited here by the idle current.
THD-wise the load current must stay well below the idle current.
With 100R current setting resistor value the idle current settles at ~6.5mA.
So the load shouldn´t be lower than app. 10kOhm to keep the load currents reasonably low.
Higher idle current could be something to wish for, but with +-12V power rails the heat power losses in the JFET and the CCS-bipolar reach approximately ~250mW each.
This is manageable with throughhole components but too much for SOT23/SOT363 SMDs.
If output voltages of 2.5Vrms suffice, then the suply rails may be lowered to +-5V.
In that case SMDs may handle even 10mA idle current well.
Suggested parts for the JFET could be BF862, LSK170C and MMBF/SST4393 in SOT23.
The BF862 beeing the lowest noise device, closely followed by the LSK170 and the 4391. As soon as Input filters are added those dominate the noise figure.
THD-wise the following is quite opposite. The 4391 simulating up to 20dB better than the BF862.
Idle current set to ~9.3mA with a 68R resistor, resulting in ~45mW heat power losses in JFET and CCS-bipolar, which the SMDs can handle.
For the CCS I suggest a Dual-NPN like the BC847BS (Diodes/NXP/MCC) or equivalents in SOT363.
Apart from DC-blocking caps and power supply caps, the circuit would be extremely tiny.
Attached is a dimensioned circuit with sim-results.
Just a single word ... cute
jauu
Calvin
the circuit in #1 is singleended class-A.
The maximum output current into the load is limited here by the idle current.
THD-wise the load current must stay well below the idle current.
With 100R current setting resistor value the idle current settles at ~6.5mA.
So the load shouldn´t be lower than app. 10kOhm to keep the load currents reasonably low.
Higher idle current could be something to wish for, but with +-12V power rails the heat power losses in the JFET and the CCS-bipolar reach approximately ~250mW each.
This is manageable with throughhole components but too much for SOT23/SOT363 SMDs.
If output voltages of 2.5Vrms suffice, then the suply rails may be lowered to +-5V.
In that case SMDs may handle even 10mA idle current well.
Suggested parts for the JFET could be BF862, LSK170C and MMBF/SST4393 in SOT23.
The BF862 beeing the lowest noise device, closely followed by the LSK170 and the 4391. As soon as Input filters are added those dominate the noise figure.
THD-wise the following is quite opposite. The 4391 simulating up to 20dB better than the BF862.
Idle current set to ~9.3mA with a 68R resistor, resulting in ~45mW heat power losses in JFET and CCS-bipolar, which the SMDs can handle.
For the CCS I suggest a Dual-NPN like the BC847BS (Diodes/NXP/MCC) or equivalents in SOT363.
Apart from DC-blocking caps and power supply caps, the circuit would be extremely tiny.
Attached is a dimensioned circuit with sim-results.
Just a single word ... cute
jauu
Calvin
Attachments
Here are some more ideas, incorporating bootstraping etc. I am just grabbing models from the LTspice library - need to try these out with some of the Linear Integrated Systems models as well.
50 Hz PSRR for all of the circuits starts at about -90 dB (middle circuit) with the LHS circuit the best at -110 dB and just gets better from there on. I'll need to do a little investigation as to why the middle circuit PSRR is lower.
I tried the middle circuit using a 2N7002 - it gave not too bad results, although the distortion was a bit higher (10ppm at 2 V out) than the JFET input versions. I would expect though that a mosfet will be noisy in practice.
The middle circuit gives a lot of scope for experimentation with the input JFET in my view, while the performance of the outer two are very good for such simple designs. However, I think you will need to choose the JFETs carefully, making sure in the RHS one that Idss of the botton current source (just shown as a current source) is below the worst case signal current. You can also accomplish that with a resistor in the source of the current source JFET.
Note, the acid test for these circuits (I have not tried it yet - that's the next job) is to test the distortion performance with an input resistance of 5k - this is the worst case situation when you have your volume pot (I am assuming 20k) set to the mid-point resistance position and the effects of the JFET input capacitance make themselves felt. For this test, you can expect low input capacitance JFETS (like the LSK489 for example) and bootstapping the drain to minimize the problem.
I have avoided a JFET+PNP CFP approach - but that is another option to explore.
Finally, I dont think the models will be entirely correct, but they do allow us to get some idea of where to tweak to improve performance - I would not put as much faith in the results as I do with bipolars - but I guess thats half the fun with JFETs.
BTW - there's a good article in the latest EDN by Bob Cordell on the new LSK489 low noise, low input capacitance JFET: http://www.edn.com/design/analog/4419861/Product-How-to--LSK489-Application-Note
50 Hz PSRR for all of the circuits starts at about -90 dB (middle circuit) with the LHS circuit the best at -110 dB and just gets better from there on. I'll need to do a little investigation as to why the middle circuit PSRR is lower.
I tried the middle circuit using a 2N7002 - it gave not too bad results, although the distortion was a bit higher (10ppm at 2 V out) than the JFET input versions. I would expect though that a mosfet will be noisy in practice.
The middle circuit gives a lot of scope for experimentation with the input JFET in my view, while the performance of the outer two are very good for such simple designs. However, I think you will need to choose the JFETs carefully, making sure in the RHS one that Idss of the botton current source (just shown as a current source) is below the worst case signal current. You can also accomplish that with a resistor in the source of the current source JFET.
Note, the acid test for these circuits (I have not tried it yet - that's the next job) is to test the distortion performance with an input resistance of 5k - this is the worst case situation when you have your volume pot (I am assuming 20k) set to the mid-point resistance position and the effects of the JFET input capacitance make themselves felt. For this test, you can expect low input capacitance JFETS (like the LSK489 for example) and bootstapping the drain to minimize the problem.
I have avoided a JFET+PNP CFP approach - but that is another option to explore.
Finally, I dont think the models will be entirely correct, but they do allow us to get some idea of where to tweak to improve performance - I would not put as much faith in the results as I do with bipolars - but I guess thats half the fun with JFETs.
BTW - there's a good article in the latest EDN by Bob Cordell on the new LSK489 low noise, low input capacitance JFET: http://www.edn.com/design/analog/4419861/Product-How-to--LSK489-Application-Note
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Hi,
the circuit in #1 is singleended class-A.
The maximum output current into the load is limited here by the idle current.
THD-wise the load current must stay well below the idle current.
With 100R current setting resistor value the idle current settles at ~6.5mA.
So the load shouldn´t be lower than app. 10kOhm to keep the load currents reasonably low.
Higher idle current could be something to wish for, but with +-12V power rails the heat power losses in the JFET and the CCS-bipolar reach approximately ~250mW each.
This is manageable with throughhole components but too much for SOT23/SOT363 SMDs.
If output voltages of 2.5Vrms suffice, then the suply rails may be lowered to +-5V.
In that case SMDs may handle even 10mA idle current well.
Suggested parts for the JFET could be BF862, LSK170C and MMBF/SST4393 in SOT23.
The BF862 beeing the lowest noise device, closely followed by the LSK170 and the 4391. As soon as Input filters are added those dominate the noise figure.
THD-wise the following is quite opposite. The 4391 simulating up to 20dB better than the BF862.
Idle current set to ~9.3mA with a 68R resistor, resulting in ~45mW heat power losses in JFET and CCS-bipolar, which the SMDs can handle.
For the CCS I suggest a Dual-NPN like the BC847BS (Diodes/NXP/MCC) or equivalents in SOT363.
Apart from DC-blocking caps and power supply caps, the circuit would be extremely tiny.
Attached is a dimensioned circuit with sim-results.
Just a single word ... cute
jauu
Calvin
Hello Calvin,
I'd put you input filter before the pot - otherwise the -3 dB cutoff is dominated by the pot position.
Since the power amp already has a low pass filter, you probably want to set the -3 dB very high on the buffer - I used 10 Ohm and 47pF so its up in the MHz range. RFI on JFETs is better than undegenerated bips so you should not have a problem in a practical circuit.
BTW - there's a good article in the latest EDN by Bob Cordell on the new LSK489 low noise, low input capacitance JFET: Product How-to: LSK489 Application Note | EDN
I just read the article, pretending to understand all of it
, and obviously this is great candidate for this circuit. If we want a simple and practical circuit it will surely benefit from the use of such high quality parts. But I do not see LSK389 listed anywhere, let alone LSK489. Would it be possible to find source for this part? Also, since I was unable to find DS for these parts I am in doubt if this is SMD part? This is new part and probably the price is high.This part is very desirable for our "practical" circuit because there are two j-fets in the same case which allows a small footprint.
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I have the same concerns. I designed a JFET input opamp (still to build and test) and used the LSK389 (I have 2 in my draw to-72 package!) or LSK489. They seem difficult to get and not at mainstream distributors. Seems to me Linear Systems need to start a web shop and take paypal or debit card - they would do well off the DIY community (Yes, I am a marketing guy . . )
The middle circuit seems for me to be the most flexible, as is Calvins - You can use many differenrt JFETs and can tailor the source CCS per the buffer JFET requirements.
re SMD - I have no problem soldering these down and actually enjoy it - but will the other builders want to use SMD? Maybe 2 layouts - SMD and TH will be needed.
)The middle circuit seems for me to be the most flexible, as is Calvins - You can use many differenrt JFETs and can tailor the source CCS per the buffer JFET requirements.
re SMD - I have no problem soldering these down and actually enjoy it - but will the other builders want to use SMD? Maybe 2 layouts - SMD and TH will be needed.
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