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Old 1st August 2013, 01:41 PM   #21
Dr_EM is offline Dr_EM  United Kingdom
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I think we posted in each others threads simultaneously!

Thanks for your input, it sounds like we're in agreement with the design criteria
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Old 1st August 2013, 01:50 PM   #22
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Good luck with the design. I will be away for a couple of weeks. Will see what direction it goes after that.
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Old 1st August 2013, 02:11 PM   #23
Dr_EM is offline Dr_EM  United Kingdom
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Thanks for your input jean-paul, hopefully the design will evolve some in that period!

With regard to the universal control of this board do we think it would be useful to include a level translator on the PCB? The CS3318 needs 3.3V logic control and it's something I've considered already since PICs are typically 5V and even if they're not, a lot of LCDs are so we need level translation somewhere.

Perhaps including a level translator IC on board and extending the input header to include a simple supply voltage input for the controlling board to connect to when desired (between 1.8-5V should then be possible) but also a jumper which can be installed when 3.3V logic is desired anyhow.
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Old 1st August 2013, 02:19 PM   #24
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Good thinking (if it needs to be as versatile as possible).

Please consider decoupling between rails as described in the data sheet and the reference design. They're not there without a reason.
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Old 1st August 2013, 05:57 PM   #25
Dr_EM is offline Dr_EM  United Kingdom
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It appears that the 74HC4050D is most suitable for the level translation task, it basically permits an over-voltage condition at the input so that 5V (or even higher) logic may be used, as may 3.3V. Compatibility with 2.5V logic isn't unrealistic looking at the typical transition voltages but couldn't be guaranteed. 1.8V logic wouldn't be permissible. Unless anyone knows of a more suitable shifter solution?

For the digital rail watchdog, a TPS3823 appears suitable. The Master Reset can be forwarded on to the control header, via the level shifter, to give conventional functionality. This just provides the guarantee that the device will enter reset when the digital rail is removed (drops below 2.93V).

I think my current de-coupling scheme is as recommended? I have used the 4x100nF parallel with 4x10uF between +V and -V rails shown in the datasheet. I just want to be certain my ground to +/-V de-coupling is also sufficient.
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Old 1st August 2013, 06:15 PM   #26
ds23man is offline ds23man  Netherlands
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AMB Laboratories DIY Audio • View topic - CS3318
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Old 1st August 2013, 08:07 PM   #27
Dr_EM is offline Dr_EM  United Kingdom
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That was a long read! Had seen some of those images around previously but not the whole thread. A lot of work been done by linux-works there, but certainly I now get the feeling that this chip is somewhat finicky

I quite like the opto-isolator solution to level conversion and perhaps the ACPL-244-500E quad isolator will suit. Does require more current from the microcontroller however and I'm not sure it gives much benefit over the 74HC4050D, is isolating the control electronics fully particularly important? This design appears to use isolation though (Toshiba TLP281-4):

M-81

It sounds like your findings are that removal/failure of the 3.3V line before the analogue while the device is powered is a condition which causes a destructive fault. The TPS3823 watchdog should be able to prevent this but it includes a 200mS delay to reinstating the reset high which might be annoying to have to work around in code. The thread references the demo board but I can't quite figure out how they're handling it on that, I think the biased transistor devices are just to drive the status LEDs?
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Old 1st August 2013, 08:21 PM   #28
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Quote:
Originally Posted by Dr_EM View Post
It sounds like your findings are that removal/failure of the 3.3V line before the analogue while the device is powered is a condition which causes a destructive fault.
I can confirm this, fried two of these ICs already!
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Old 1st August 2013, 08:35 PM   #29
Dr_EM is offline Dr_EM  United Kingdom
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Oh dear, and they're not cheap either, especially when mounted on a PCB like this where you're unlikely to remove it without damaging the board too.

We'll need a failsafe way to protect the chip from this condition. Provided the analogue section is fully shut down when the device is reset then it's quite simple, but I might feel safer using analogue regulators with a shutdown feature which is then activated whenever there is no 3.3V present. Will be a bit of a hunt to find those I think, the negative one at least.

maxw, how are you using your ICs now or did you abandon because of their vulnerability?
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Old 1st August 2013, 08:37 PM   #30
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Quote:
Originally Posted by Dr_EM View Post
I think my current de-coupling scheme is as recommended? I have used the 4x100nF parallel with 4x10uF between +V and -V rails shown in the datasheet. I just want to be certain my ground to +/-V de-coupling is also sufficient.
It is. Just checked again.
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