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Old 24th November 2012, 04:14 PM   #31
dadod is offline dadod  Croatia
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Originally Posted by keantoken View Post
Great!
Thanks Kean for your great help!
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Old 24th November 2012, 06:48 PM   #32
bcarso is offline bcarso  United States
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Interesting thread.

Have you considered/examined the distortion associated with the buffer amps? In particular, what is the effect of the voltage-dependent Cgd of the input devices on the left? As drawn the source impedance is assumed to be zero except for the effect of C1. Probably, typical line-level sources will be low enough, although not zero.

Buffering the output of the conveyor, on the other hand, will be affected by the relatively high value of its output termination resistor, R1 in the "Clipping4" schematic.

The composite JFET-bipolar feedback pairs will do a pretty good job of bootstrapping out the Cgs at least.

And I like the introduction of base current recapture, as Wurcer calls it (historically, now dating back to F. S. Boxall), which works progressively better as the collector of the auxiliary transistor feeds a higher impedance (in this case the collectors of Q5 and Q7).

Brad
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Old 24th November 2012, 08:54 PM   #33
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Originally Posted by bcarso View Post
Interesting thread.

Have you considered/examined the distortion associated with the buffer amps? In particular, what is the effect of the voltage-dependent Cgd of the input devices on the left? As drawn the source impedance is assumed to be zero except for the effect of C1. Probably, typical line-level sources will be low enough, although not zero.

Buffering the output of the conveyor, on the other hand, will be affected by the relatively high value of its output termination resistor, R1 in the "Clipping4" schematic.

The composite JFET-bipolar feedback pairs will do a pretty good job of bootstrapping out the Cgs at least.

And I like the introduction of base current recapture, as Wurcer calls it (historically, now dating back to F. S. Boxall), which works progressively better as the collector of the auxiliary transistor feeds a higher impedance (in this case the collectors of Q5 and Q7).

Brad
Here is FFT at 1kHz with 100k source impedance. Why do you say "high value of R1", it is just 560 ohm?
Damir
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Old 24th November 2012, 09:09 PM   #34
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This is the Gain.
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Old 24th November 2012, 09:12 PM   #35
bcarso is offline bcarso  United States
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Here is FFT at 1kHz with 100k source impedance. Why do you say "high value of R1", it is just 560 ohm?
Damir
I didn't see the value on the one schematic I referenced, sorry.

BTW, you are running the JFETs at rather high |Vdg|. In the case of the 2SJ74, the maximum rating is 25V Fred Forsell has gotten away with exceeding these ratings in his JFET amps, but agrees that it is risky.

My sims of the first buffer amp driving a comparable resistive load (note that the actual loading by the current conveyor is variable somewhat with signal current and hence will be another distortion mechanism I exclude) show low distortion at 1kHz as well (1V peak, 500 ohm source Z).

Things are still o.k. with 20kHz although the majority of the distortion is now at the input (-112.4dBr input, -112.0dBr output, harmonics included to 9th).

With 10k as the source resistance, the same situation holds with the majority of the distortion due to variable input C (-86.5dBr at input, -86.4dBr at the output). Noted as well: the distortion is primarily 2nd, due to the considerable difference in capacitances between the SK170 and the SJ74.

If one goes about removing most of the gate-drain C effects, performance should improve drastically. With Csanky-style bootstrapped cascoding one can also alleviate the excess voltage issues for the P part. Some small lumped capacitance at the input will probably be needed to reduce high-frequency peaking.

Brad
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Old 24th November 2012, 09:43 PM   #36
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I know, all distortion's coming from the buffers. I was thinking how to improve that with a kind of cascoding. What is Csanky-style bootstrapped cascoding?
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Old 24th November 2012, 09:58 PM   #37
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Walt Jung posted recently about Csanky and gave some references I believe. I'll try to find the post.

Basically, it's just cascoding JFETs and returning the "upper" device's gate to the "lower" device's source. If the latter source is grounded it just becomes a standard JFET cascode, working best when the upper device has a higher pinchoff voltage. When there is impedance in the source then the connection helps more, as the capacitative displacement currents from the upper FET are recycled to some extent and have the effect of reducing the output capacitance (and hence its distortion contribution due to voltage variation) of the upper device.
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Old 24th November 2012, 10:06 PM   #38
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Oh yes I know it, Borberly used it a lot, is it not?
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Old 24th November 2012, 10:18 PM   #39
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Oh yes I know it, Borberly used it a lot, is it not?
Yes, very much so. I remember puzzling about it initially. Erno typically cascaded SK170s with SK246, SJ74 with SJ103.
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Old 24th November 2012, 10:34 PM   #40
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As I don't have the models nor real fets with a higher pinchoff voltage I did it in this way. Distortion is down but not so much as I expected.
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